Table 16. eSDHC system-level checklist
Item
Completed
3.3 V/1.8 V
3.3 V/1.8 V
eMMC
card
LS1046A/LS1026A
CMD, DAT[0], DAT[1:3], CLK, CD
In DDR mode, all input signals are sampled
with respect to SYNC_IN.
SDHC_CLK_SYNC_OUT
SDHC_CLK_SYNC_IN
Figure 16. DDR mode
5.7 Global interrupt controller (GIC) recommendations
Note that the GIC pins in LS1046/LS1026A are distributed over several voltage domains.
5.7.1 GIC pin termination recommendations
Table 17. GIC pin termination checklist
Signal name
I/O type
Used
Not used
Completed
IRQ[0:2]
I
Ensure these pins are driven in the
non-asserted state.
These pins should be tied to
nonasserted state through a 2-10 kΩ
resistor.
• When non-asserted state is high,
tied to OV
DD
• When non-asserted state is low,
tied to GND
IRQ[3:10]
I
Ensure these pins are driven in the
non-asserted state.
The functionality is determined by the
IRQ_BASE and IRQ_EXT field in the
reset configuration word
(RCW[IRQ_BASE] and
RCW[IRQ_EXT]).
These pins should be tied to
nonasserted state through a 2-10 kΩ
resistor.
• When non-asserted state is high,
tied to DV
DD
• When non-asserted state is low,
tied to GND
or else programmed as GPIOs and
ouputs.
IRQ[11]
I
This pin should be tied to nonasserted
state through a 2-10 kΩ resistor.
Interface recommendations
QorIQ LS1046A Design Checklist , Rev. 2, 06/2020
26
NXP Semiconductors
