The reset configuration signals are multiplexed with other functional signals. The values on these signals during reset are
interpreted to be logic one or zero, regardless of whether the functional signal name is defined as active-low. The reset
configuration signals have internal pull-up resistors so that if the signals are not driven, the default value is high (a one), as
shown in the table below. Some signals must be driven high or low during the reset period. For details about all the signals
that require external pull-up resistors, see the applicable device data sheet.
Table 6. LS1046A reset configuration signals
Configuration Type
Functional Pins
Comments
Reset configuration word (RCW) source
inputs cfg_rcw_src[0:8]
IFC_AD[8:15]
IFC_CLE
They must be set to one of the valid RCW
source input option. The 512-bit RCW
word has all the necessary configuration
information for the chip. If there is no valid
RCW in the external memory, it can be
programmed using the Code Warrior or
other programmer. The JTAG configuration
files (path: CWInstallDir
\CW4NET_v2019.01\CW_ARMv8\Config
\boards) can be used in the following
situations:
• target boards that do not have RCW
already programmed
• new board bring up
• recovering boards with blank or
damaged flash
IFC external transceiver enable polarity
select (cfg_ifc_te)
IFC_TE
Default is "1"
DRAM type select (cfg_dram_type)
IFC_A[21]
The reset configuration pin selects the
proper IO voltage.
• 1=Reserved
• 0=DDR4 (1.2 V)
Ensure the selected value matches DDR4
General-purpose input (cfg_gpinput[0:7]) IFC_AD[0:7]
Default "1111 1111", values can be
application defined
"Single Oscillator Source" clock select.
This field selects between SYSCLK
(Single ended) and DIFF_SYSCLK/
DIFF_SYSCLK_B (differential) inputs.
(cfg_eng_use0)
IFC_WE0_B
0=DIFF_SYSCLK/
DIFF_SYSCLK_B(differential)
1=SYSCLK (single ended)
Default selection is single ended SYSCLK;
"1"
"Single Oscillator Source" clock.
This field indicates whether on-chip
LVDS termination for differential clock is
enabled or disabled.
configuration (cfg_eng_use1)
IFC_OE_B
0 = Disabled (MUST make sure that
External termination pads of
DIFF_SYSCLK/DIFF_SYSCLK_B have
proper termination)
1 = Enabled (default)
Default is "1".
It is recommened to keep provision for
optional pull-down resistor on board.
"Single Oscillator Source" clock
configuration (cfg_eng_use2)
IFC_WP0_B
Default is "1". Reserved.
Power design recommendations
QorIQ LS1046A Design Checklist , Rev. 2, 06/2020
14
NXP Semiconductors
