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NXP Semiconductors QorIQ LS1026A, Manual

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Table 1. Helpful tools and references (continued)

ID

Name

Location

AN4871

Assembly Handling and Thermal Solutions for Lidless Flip Chip Ball Grid
Array Packages

www.nxp.com

AN5097

Hardware and Layout Design Considerations for DDR4 SDRAM Memory
Interfaces - Application Note

www.nxp.com

AN4311

SerDes Reference Clock Interfacing and HSSI Measurements
Recommendations

www.nxp.com

AN5348

Using QorIQ LS1046ARDB in PCIe Endpoint Mode

www.nxp.com

Software tools

CodeWarrior Development Software for ARM® v8 64-bit based QorIQ LS-
Series Processors

www.nxp.com

Software Development Kit for LS1046A

www.nxp.com

Hardware tools

CodeWarrior TAP

www.nxp.com

QorIQ LS Processor Probe Tips for CodeWarrior TAP

www.nxp.com

QorIQ LS1046A reference design board

www.nxp.com

Models

IBIS

To ensure first path success, NXP strongly recommends using the IBIS
models for board-level simulations, especially for SerDes and DDR
characteristics.

Contact your NXP
representative

BSDL

Use the BSDL files in board verification.

Contact your NXP
representative

Flotherm

Use the Flotherm model for thermal simulation. Especially without forced
cooling or constant airflow, a thermal simulation should not be skipped.

Contact your NXP
representative

Available training

-

Our third-party partners are part of an extensive alliance network. More
information can be found at www.NXP.com/alliances.

www.nxp.com/alliances

-

Training materials from past Smart Network Developer's Forums and NXP
Technology Forums (FTF) are also available at our website. These training
modules are a valuable resource for understanding the chip.

www.nxp.com/alliances

NOTE

Design requirements in the device datasheet supersede requirements mentioned in design
checklist and design requirements mentioned in design checklist supersede the design/
implementation of the NXP reference design (RDB) system.

3.2 Product revisions

This table lists the system version register (SVR) and ARM core main ID register (TRCIDR1) values for the various chip
silicon derivatives.

Simplifying the first phase of design

QorIQ LS1046A Design Checklist , Rev. 2, 06/2020

4

NXP Semiconductors

Summary of Contents for QorIQ LS1026A

Page 1: ...TE This document applies to the LS1046A and LS1026A devices For a list of functionality differences see the appendices in QorIQ LS1046A Reference Manual document LS1046ARM 2 Before you begin Ensure yo...

Page 2: ...CIe 3 0 PCIe 3 0 PCIe 3 0 SD SDIO eMMC DMA Core Complex Accelerators and Memory Control Basic Peripherals Interconnect and Debug Networking Elements 4 Lane 10 GHz SerDes Queue Manager Buffer Manager P...

Page 3: ...ocumentation some of which may be available only under a non disclosure agreement NDA Contact your local field applications engineer or sales representative to obtain a copy Table 1 Helpful tools and...

Page 4: ...ve BSDL Use the BSDL files in board verification Contact your NXP representative Flotherm Use the Flotherm model for thermal simulation Especially without forced cooling or constant airflow a thermal...

Page 5: ...I O supply IFC SPI GIC IRQ 0 1 2 Temper_Detect System control and power management SYSCLK DDR_CLK DIFF_SYSCLK GPIO2 GPIO1 eSDHC 4 7 VS DAT123_DIR DAT0_DIR CMD_DIR SYNC Debug JTAG RTC FTM5 6 7 POR sig...

Page 6: ...CGA2 CPU cluster group A PLL2 supply 1 8 V independent supplies derived from board 1 8 V Must remain powered AVDD_PLAT Platform PLL supply 1 8 V independent supplies derived from board 1 8 V Must rema...

Page 7: ...er supply filtering section of this table If SerDes is enabled ensure the PLL filter circuit is applied to the respective AVDD_SDm_PLLn pins Otherwise a filter is not required Even if an entire SerDes...

Page 8: ...pply which can regulate its output voltage very accurately despite changes in current demand from the chip within the regulator s relatively low bandwidth Several bulk capacitors must be distributed a...

Page 9: ...the SerDes PLL To ensure stability of the internal clock ensure the power supplied to the PLL is filtered using a circuit similar to the one shown in the following figure The recommended solution for...

Page 10: ...imary SVDD power supply filter circuit 2 2 F 2700 PF Bulk capacitors Decoupling capacitors SVDD VDD or linear or low noise switching regulator GRM155R71H272KA01 GRM155R60J225KE95 BLM18KG121TN1 Figure...

Page 11: ...se coupled from nearby circuits Located at each pin should have a decouple capacitor such as 0 1 F USB_HVDD may be supplied by a linear or low noise switching regulator which may be the system wide 3...

Page 12: ...se either one as they see best fit their needs but the primary NFM type filter has two advantages lower DC droop and easier layout than the ferrite bead solution 2 2 F 2 2 F VDD Bulk capacitors Decoup...

Page 13: ...ull up and pull down resistors to configure the POR pins is to use a PLD or similar device that drives the configuration signals to the chip when PORESET_B is asserted The PLD must begin to drive thes...

Page 14: ...situations target boards that do not have RCW already programmed new board bring up recovering boards with blank or damaged flash IFC external transceiver enable polarity select cfg_ifc_te IFC_TE Def...

Page 15: ...ck input to LS1046A For bringing up a new board when no valid RCW or bootloader is available and onboard flash is not supported in CodeWarrior then refer to AN12081 5 Interface recommendations This se...

Page 16: ...eft unconnected Unused MCK pins can be disabled using DDRCLKDR register D1_MCK_B 0 1 O Ensure these pins are terminated correctly May be left unconnected D1_MCS 0 3 _B2 O Must be properly terminated t...

Page 17: ...ion to prevent an excessive overshoot 3 When DDR4 Discrete or RDIMM DRAM is soldered on the board and two chip selects are used and the second chip select is bit swizzling meaning bits mapping from CS...

Page 18: ...n the value of the net at reset a pull up or active driver is needed IFC_A 22 27 I O Connect as needed These pins can be left unconnected IFC_AD 0 15 I O These pins are reset configuration pins They h...

Page 19: ...drive this pin to a safe state during reset IFC_CLE O This pin is a reset configuration pin It has a weak 20 k internal pull up P FET that is enabled only when the processor is in its reset state This...

Page 20: ...y of LPUART1_CTS_B is determined by the UART_EXT field in the reset configuration word These pins should be pulled high through a 2 10 k resistor to DVDD or else programmed as GPIO and output LPUART 2...

Page 21: ...n checklist Signal Name I O type Used Not used Completed IIC1_SDA I O Tie these open drain signals high through a nominal 1 k resistor to DVDD Optimum pull up value depends on the capacitive loading o...

Page 22: ...S1026A SD 3 0 DS Default Speed Yes Yes Yes Yes Neither supported by the SD standards nor by the LS1046A LS1026A device HS High Speed Yes Yes Yes Yes SDR12 No No Yes Yes SDR25 No No Yes Yes SDR50 No No...

Page 23: ...t SDHC_CD_B I These pins should be pulled high through 10 100 k resistors to DVDD The functionality is determined by the SDHC field in the reset configuration word RCW IIC2_EXT This pin should be pull...

Page 24: ...LK_SYNC_OUT and SDHC_CLK_SYNC_IN should be routed as close as possible to the card with minimum skew with respect to SD_CLK 5 When using 8 bit MMC eMMC configuration EVDD and OVDD should be set at sam...

Page 25: ...Connections DS HS HS200 Modes at 1 8 V card The 8 bit eMMC interface requires EVDD and OVDD configured at 1 8V 1 8 V 1 8 V eMMC CARD 1 8 V LS1046A LS1026A CMD DAT 0 DAT 1 7 CLK CD Figure 15 DS HS and...

Page 26: ...n the non asserted state These pins should be tied to nonasserted state through a 2 10 k resistor When non asserted state is high tied to OVDD When non asserted state is low tied to GND IRQ 3 10 I Ens...

Page 27: ...n resistor is strongly recommended This pin should be pulled high through a 2 10 k resistor to VDD 1 0 V TA_TMP_DETECT_B I If a tamper sensor is used it must maintain the signal at the specified volta...

Page 28: ...k resistor to OVDD Alternately EVT_B 9 can be programmed as output through EPU_EPEVTCR register early in boot code and left unconnected JTAG_BSR_VSEL1 I It is advised that boards are built with the a...

Page 29: ...protocol selected by the RCW settings If the PLL is unused pull down to GND SD1_REF_CLK2_N SD1_REF_CLK2_P I SD1_RX 0 3 _N I Ensure pins are correctly terminated for the interface type used If the SerD...

Page 30: ...tocol 7 When LS1046A is used as an EP on motherboards it is recommended to use the PCIe express clock from the PCIe slot as SerDes reference clock for LS1046A This ensures that 300ppm reference clock...

Page 31: ...s condition the Rx Equalization Boost bit for all the lanes in use should be set to 0b during the Pre boot Initialization PBI stage Since the Rx Equalization Boost bit is defined in different SerDes r...

Page 32: ...pins should be left floating USB_DRVVBUS O VBUS power enable For example if an external hub is used it can handle this signal The functionality of the USB_DRVVBUS signal is determined by the RCW USB_D...

Page 33: ...nect These pins can be left floating USB3_PWRFAULT I Indicates that a VBUS fault has occurred For example if an external hub is used it can handle this signal The functionality of the USB_PWRFAULT sig...

Page 34: ...s pin to LVDD with a suitable resistor The value of pull up resistor depends on input impedance of all the peripherals connected on EMI1 bus More the peripherals or more the impedance stronger the pul...

Page 35: ...peripherals on EMI bus might have their EMI1_MDIO pins configured as open drain The value of pull up resistor depends on total input impedance of all the peripherals connected EMI2_MDC O The functiona...

Page 36: ...normal functional mode the EMI2_MDIO will be actively driven A pull up resistors might still be required as the peripherals on EMI bus might have their EMI2_MDIO pins configured as open drain The val...

Page 37: ...X_CLK1252 I NOTE 1 This pin requires an external 1 k pull down resistor to prevent PHY from seeing a valid Transmit Enable before it is actively driven 2 Either of the EC1_GTX_CLK125 or EC2_GTX_CLK125...

Page 38: ...hen booting from QSPI Once the workaround is applied HRESET_B can no longer be used The following are the modes which can be used without applying the workaround SDHC interface is not used at all SDHC...

Page 39: ...nality of these signals is determined by the RCW UART_BASE RCW UART_EXT field in the reset configuration word GPIO1_ 23 31 IO The functionality of these signals is determined by the RCW IRQ_EXT and RC...

Page 40: ...ionality of these signals is determined by the RCW EM2 field in the reset configuration word For all GPIOx pins When programmed as outputs no termination is required GPIO4_ 2 3 IO The functionality of...

Page 41: ...am as a GPIO and as an output FTM2_EXTCLK I FTM2_FAULT I FTM2_QD_PHA I FTM2_QD_PHB I 5 20 FTM3 pin termination recommendations Table 30 FTM3 pin termination checklist Signal Name IO type Used Not Used...

Page 42: ...M4_FAULT I FTM4_QD_PHA I FTM4_QD_PHB I 5 22 FTM5 pin termination recommendations Table 32 FTM5 pin termination checklist Signal Name IO type Used Not Used Completed FTM5_CH 0 1 IO The functionality of...

Page 43: ...register SCFG_RCWPMUXCR0 Program as a GPIO and as an output 5 26 IEEE 1588 recommendations 5 26 1 IEEE 1588 pin termination recommendations Table 36 IEEE 1588 pin termination checklist Signal Name I O...

Page 44: ...r on reset This pin should be pulled high through a 2 10 k resistor to OVDD and must not be pulled down during power on reset NOTE 1 If on board programming of NOR boot flash QSPI boot flash or SD car...

Page 45: ...JTAG port of these processors allows a remote computer system typically a PC with dedicated hardware and debugging software to access and control the internal operations of the processor The ARM Cort...

Page 46: ...ensive option is to leave the ARM Cortex 10 pin header unpopulated until needed Correct operation of the JTAG interface requires configuration of a group of system control pins as demonstrated in Figu...

Page 47: ...ct is an optional board feature Check with 3rd party tool vendor 2 This switch is included as a precaution for BSDL testing The switch should be open during BSDL testing to avoid accidentally assertin...

Page 48: ...d these pins should be connected to a 100 MHz differential clock generator The LVDS receiver for differential sysclk input requires a minimum of 50mV of common mode voltage so AC couplings cannot be u...

Page 49: ...ck mode In this mode single onboard oscillator can provide the reference clock 100 MHz to the following PLLs Platform PLL Core PLLs USB PLL DDR PLL SerDes PLLs The reset configuration field identifies...

Page 50: ...1_P SD2_REF_CLK1_N RCW SRDS_REFCLK_SEL_S1 RCW SRDS_REFCLK_SEL_S2 LVDS Onboard oscillator 100 MHz DDR PLL MUX MUX MUX MUX MUX FMAN MAC Differential outputs SCFG_ECGTXCMCR CLK_SEL Figure 19 Single oscil...

Page 51: ...SYSCLK_B can be selected to provide primary clock to the chip Although it is a Low Voltage Differential Signaling LVDS type clock driver but it has AC DC characteristics identical to the SerDes refere...

Page 52: ...eiver 33 CLK_Out 100 DIFF_SYSCLK_B NXP device Figure 21 Interfacing with HCSL clock driver Reference only Connection with LVDS Clock driver LVDS CLK Driver chip CLK_Out Clock 100 differential PWB trac...

Page 53: ...LVPECL clock driver Reference only Single Ended Connection with Clock driver The DIFF_SYSCLK_B should be terminated to OVDD 2 Single ended CLK driver chip OVDD 2 Clock 100 differential PWB trace DIFF_...

Page 54: ...kage or thermal data not available in this document can be obtained from your local NXP sales office Use this recommended board attachment method to the heat sink 1 The processor heat sink must be con...

Page 55: ...spatial volume mass attachment method assembly and cost 2 The performance of the thermal interface materials improves with increased contact pressure the thermal interface vendor generally provides a...

Page 56: ...sink attach material or thermal interface material and finally to the heat sink The junction to case thermal resistance is low enough that the heat sink attach material and heat sink thermal resistan...

Page 57: ...on signals sampled at reset Corrected typo HRESET_REQ_B and added note referring AN12081 in Hard coded RCW Corrected typo fields and LPUART 1 3 _RTS_B in LPUART pin termination recommendations Changed...

Page 58: ...accepts no liability for any vulnerability that is discovered Customers should implement appropriate design and operating safeguards to minimize the risks associated with their applications and produc...

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