NXP Semiconductors
PT2001SWUG
PT2001 programming guide and instruction set
PT2001SWUG
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User guide
Rev. 3.0 — 29 April 2019
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mul
Description:
Multiplies the value contained in the op1 register with the value contained in op2 register
and places the result in the reg32 register. The reg32 register is the concatenation of the
multiplication result registers mh and ml:
mh contains the 16-MSB ml contains the 16-MSB
The multiplication requires 32 ck clock cycles to be completed.
Operation:
(Source1) x (Source2) → (Destination)
Assembler syntax:
mul op1 op2;
Operands:
•
op1– One of the registers listed in the operand
Section 3.1.2 "AluGprIrReg subset"
•
op2– One of the registers listed in the operand
Section 3.1.2 "AluGprIrReg subset"
Condition register:
•
MO – Multiplication shift overflow
•
ML – Multiplication shift precision loss
•
OD – Operation complete
Table 70. mul instruction format
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
1
0
1
1
0
1
1
0
op2
op1
