
NXP Semiconductors
UM191812
PN544 C2 User Manual
191812
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
User Manual
Rev. 1.2 — 2010-06-16
29 of 172
(3) T
ic
: inter-character timeout
Fig 21. Sample I
2
C Host to PN544 Communication
7.4.7.2 Example: Communication from Slave to Master (PN544 to Host)
The PN544 shall notify via the IRQ line that it wants to transmit data. The host shall now
start to address the PN544 and shall set the direction to READ. The PN544 shall now
convey the pending data to the host.
If the host performs a read request even if the chip does not have to send anything (i.e.
the chip did not ask for a clock or the data turned out to be for some reason irrelevant),
the chip shall transmit bytes containing the value (0xFF)h until the clock has been turned
off.
A/R
LEN
H
B
LEN
B
1
Regular Frame Transfer: PN544 -> Host
PN544 requests a
transfer
Host addresses the
PN544 and sets the
direction to R
PN544 sends the
length of the frame
CRC
1
CRC
2
Host knows how often to
apply the clock
IRQ
SDA
SCL
Data has been sent, IRQ
is reset.
If the time between two bytes is bigger than T
IC_max
, the buffer
will be invalidated and the state machine will be reset.
If the PN544 requests a transfer
but the host sets the direction to
W, the IRQ will remain HIGH.
CRC is automatically appended
after the TCM is finished
If the hosts sends
more clocks zeros
will be sent.
Fig 22. I
2
C PN544 to Host Regular Transfer
Note: At the end of a received frame, the IRQ is set to logic low and goes to high at the
beginning of the following frame.