NXP Semiconductors
UM191812
PN544 C2 User Manual
191812
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User Manual
Rev. 1.2 — 2010-06-16
139 of 172
9.16 Type B PICC
This paragraph explains in which ways the PN544 can behave like a Type B card.
9.16.1 Type B PICC over SWP (UICC as a Type B card)
The Type B card emulation can be located in the UICC connected to PN544 over SWP
link.
Refer to paragraph SWP.
9.16.2 Type B PICC over host link (I2C, SPI, HSU) (host as a Type B card)
The Type B card emulation can be located in the host connected to PN544 over I2C, SPI
or HSU link.
The host is not allowed to transmit a PUPI. The PUPI in that case is randomly generated
by the PN544.
9.16.3 Multiple Type B PICC
PN544 cannot emulate two type B cards at the same time.
It is not possible to emulate at the time a Type B card in the UICC and in the host. (The
Create Pipe, on an already in use card RF gate, will return an error). The host decides to
allow or not the UICC to emulate a Type B card. If it allows the UICC emulate a Type B
card, then it cannot itself emulate a Type B card.
Note: Refer to ‘
Type A PICC
’ flowcharts to have an overview of system exchanges.
(Same HCI events/registry/commands are required on
Type B Card RF Gate
)
Note: In Type B PICC mode, the HIGHER_LAYER_RESPONSE registry has a maximum
size of 31 bytes. PN544 does not support HIGHER_LAYER_RESPONSE registry size
between 32 and 252 bytes.
No visible impact is foreseen at end user level.
ETSI/HCI test specification Rev2.4 proposes a test with 10 bytes.