NXP Semiconductors
UMxxxxx
Install Guide
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Preliminary 1
— September 6, 2013
© NXP B.V. 2013. All rights reserved.
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7.1
Theory of Operation
Two identical Bus Buffer devices are connected in series between the Bus1 and Bus2 segments on the
Fm+ Development Board (OM13260), each Bus Buffer has two identical channels, one for I2C Clock
(SCL) and the second for I2C Data (SDA) only one channel will be described in detail.
Each PCA9617A Bus Buffer device has two power supply connections; VCC(A) and VCC(B) to allow
voltage level shifting between one I2C Bus segment and another I2C Bus segment. Jumpers on the Bus
Buffer Board (OM13398) select the voltage source of each of the two device power supplies. To
demonstrate the voltage level translator ability the link between the two Bus Buffers is supplied from a
variable voltage regulator, which in turn can be set by the user anywhere between 1.0V and 3.2V.
The pull up resistor on the Low Voltage Bus section is selected by jumpers.
7.2
Circuit Description
The schematic diagram has multiple sheets. For clarification only fragments of the schematic are
shown here. The full schematic should be downloaded if required. The following pages are divided in to
several sections covering the Bus1 Bus Buffer, Bus2 Bus Buffer, Supply select jumpers, Variable Voltage
Regulator, and Connectors. A block diagram will assist understanding. See figure 7.3
Fig 7.3 Block Diagram for the Bus Buffer Board (OM13398)
Summary of Contents for OM13260
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