Figure 3. External crystal circuit
The load capacitors are dependent on the specifications of the crystal and on the board capacitance. It is recommended to
have the crystal manufacturer evaluate the crystal on the evaluation board / PCB.
3.1 Frequency Modulated PLL (FMPLL)
The FMPLL allows the user to generate high speed system clocks from a 4MHz to 40MHz input clock. Futhermore, the
FMPLL supports programmable frequency modulation of the system clock. The PLL has the following major features:
• Input clock frequency from an 4MHz to 40MHz
• Voltage controlled oscillator (VCO) range from 256MHz to 512MHz
• Reduced frequency divider (RFD) for reduced frequency operation without forcing the PLL to re-lock
• Frequency modulated PLL
• Modulation enabled/disabled through software
• Triangle wave modulation
• Programmable modulation depth (±0.25% to ±4% deviation from center frequency)
• Programmable modulation frequency dependent on reference frequency
• Self-clocked mode (SCM) operation
• Input supply : same as core supply : 1.2V
The MPC56xx devices can use either the on-chip oscillator with an external crystal or an external reference clock as the
reference clock to the device. This reference is qualified in multiple manners before the PLL will begin lock operation. The
“pre” FMPLL circuitry consists of an automatic level-controlled amplifier, a comparator, a loss of clock detector, and a
predivider.
Clock Circuity
Hardware Design Guide, Rev. 0, 2012
8
Freescale Semiconductor, Inc.
