NXP Semiconductors MCF5235 Reference Manual Download Page 9 | Manualshive

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NXP Semiconductors MCF5235 Reference Manual Download Page 9

Revision History

MCF5235 Reference Manual Errata, Rev. 2.2

Freescale Semiconductor

9

The below errata were added for MCF5235RM Revision 2

2

• Added QSPI_CS/SD_CKE pin location errata.

08/2006

2.1

• Added RMON_R_DROP counter errata.

11/2006

2.2

• Added various core, EMAC, cache, SRAM and debug chapter errata.
• Added CLKIN to CLKOUT errata.
• Added FEC MIB counter memory map errata.
• Added “Duplicate Frame Transmission” section to FEC chapter.
• Added DACRn[CBM] field description note.
• Added secondary wait state timing diagram errata.
• Added SKMR[CTRM,DKP] errata.
• Added CIM/CCM errata.
• Added EPDDR figure errata.
• Added DMA figure overbars errata.
• Added DMA external request and acknowledge operation section errata.
• Added DMA SAA bit errata.
• Added IPSBAR note in SCM chapter.
• Added global IACK space errata.

05/2007

Table 3. Revision History Table (continued)

Rev. Number

Substantive Changes

Date of Release

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Summary of Contents for MCF5235

Page 1: ...MCF5235 Reference Manual order number MCF5235RM For convenience the addenda items are grouped by revision Please check our website at http www freescale com coldfire for the latest updates The current...

Page 2: ...CR fields to R W since they may be read via the debug module Table 5 5 Page 5 10 For split instruction data cache entry swap text in parantheses in the description field Instruction cache uses the upp...

Page 3: ...one of the global LnIACK registers returns the vector for the highest priority unmasked interrupt within a level for all interrupt controllers There is no global SWIACK register However reading the S...

Page 4: ...the following subsection entitled Duplicate Frame Transmission The FEC fetches transmit buffer descriptors TxBDs and the corresponding transmit data continuously until the transmit FIFO is full It do...

Page 5: ...output pin may be disabled to lower power consumption via the SYNCR DISCLK bit The external CLKOUT pin function is enabled by default at reset Table 7 3 Page 7 7 Footnote should read In 1 1 mode for...

Page 6: ...e 9 9 Remove RCON 7 6 10 from clock mode default configuration field Footnote added There is no default configuration for clock mode selection The actual values for the CLKMOD pins must always be driv...

Page 7: ...available when using an external clock source Section 26 4 1 2 2 Page 26 19 Change equation to Baudrate fextc 16 or 1 since the 16 bit divider is not available when using an external clock source Sec...

Page 8: ...n Chapter 32 07 2005 1 4 Added pin F10 errata in Chapter 2 and 12 Added ERXER and ETXER direction errata in Chapter 2 and 12 Added default output pad drive strength errata Added Table 7 3 footnote err...

Page 9: ...MIB counter memory map errata Added Duplicate Frame Transmission section to FEC chapter Added DACRn CBM field description note Added secondary wait state timing diagram errata Added SKMR CTRM DKP erra...

Page 10: ...particular purpose nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including with...

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