MCF5235 Reference Manual Errata, Rev. 2.2
Errata for Revision 1.1
Freescale Semiconductor
6
Section 8.3.2.20/Page 8-10 The FlexCAN module does not support self-wake or auto-power save modes. Therefore,
change the following:
• Remove second paragraph.
• Change second sentence in first paragraph to “The module has 18 interrupt sources (16
sources due to message buffers and 2 sources due to bus-off and error).”
• Change STOP bit to MDIS bit throughout.
• Change MCR to CANMCR throughout.
• Remove third bullet under “Exiting stop mode is done in one of the following ways”
• Remove second sentence in second bullet under “Recommendations for...”
• Remove bullets 4-8 under “Recommendations for...”
• Remove last 3 paragraphs and last bullet list.
Table 9-1/Page 9-2
Reset config override signals should be D[25:24, 21:19, 16] instead of D[26:24, 21, 19:16].
Section 9.2.3/Page 9-3
Section title should be “D[25:24, 21:19, 16]...” instead of “D[26:24, 21, 19:16]...”
Figure 9-3/Page 9-5
Unreserved RCON register bits should be read only.
Table 9-7/Page 9-8
Reset config override signals should be D[25:24, 21:19, 16] instead of D[26:24, 21, 19:16].
Table 9-8/Page 9-8
Chip mode heading should be D16 only, since D26 & D17 have no affect on the selected
chip mode. Master mode (default) is selected by asserting D16. Deasserting D16 during
RCON assertion at reset places the device in a reserved mode.
Table 9-8/Page 9-8
Remove “RCON[2]=0” in boot device default configuration field.
Table 9-8/Page 9-8
Default output pad drive strength should be partial instead of full.
Table 9-8/Page 9-9
Remove “RCON[7:6]=10” from clock mode default configuration field. Footnote added:
“There is no default configuration for clock mode selection. The actual values for the
CLKMOD pins must always be driven during reset. Once out of reset, the CLKMOD pins
have no effect on the clock mode selection.”
Table 9-8/Page 9-9
“Chip select configuration“ entry for setting D[25:24]=11, should read “PADDR[7:5] =
CS[6:4]” instead of “PADDR[7:6] = CS[6:4]”
Table 9-8/Page 9-9
Footnote #2: Changed which pins do not affect reset configuration: “The D[31:26, 23:22,
18:17, 15:0] pins do not affect reset configuration.”
Section 9.4.2/Page 9-9
The MODE field is in the RCON register instead of the CCR.
Table 9-9/Page 9-9
Remove MODE[2] and MODE[1] columns since the MODE field is only one bit wide and
also D26 and D17 have no affect on chip configuration mode selection.
Table 12-1/Page 12-7
ERXER direction should be input, ETXEN direction should be output.
Table 12-1/Page 12-9
For 196BGA package, change pin F10 from OVDD to VSS.
Table 12-10/Page 12-22
Change an erroneous TSIZ1 to TSIZ0 in the PAR_TSIZ0 entry.
Figure 14-9/Page 14-16
DACKn is only asserted for a single clock cycle. All other signals (TS, CS, TA, R/W, and
A[23:0] are subsequently moved one cycle sooner.
Throughout Chapter 16
Replace instances of D[19:18] with D[20:19].
Section 16.2.1/Page 16-1
An overbar should be placed over the CS[7:0] in the section heading.
The last sentence should read: “Port size for CS0 is configured by the logic levels of
D[20:19] when RSTOUT negates and RCON is asserted.”
Table 16-6/Page 16-9
In the CSMRn[BAM] bit description, the first example BAM bit setting is incorrect. Change
from 0x0008 to 0x0001.
Table 2. MCF5235RM Rev 1.1 Errata (continued)
Location
Description