MCF5235 Reference Manual Errata, Rev. 2.2
Revision History
Freescale Semiconductor
8
3
Revision History
Table 3
provides a revision history for this document.
Table 3. Revision History Table
Rev. Number
Substantive Changes
Date of Release
1.0
• Initial release.
10/2004
1.1
• Added DACKn overbar errata.
• Added Byte Strobe errata.
• Added LPCR[2:0] descriptions.
• Added various RCON errata.
• Added chip mode errata.
• Added DACKn asserted for a single cycle errata.
11/2004
1.2
• Added D0 & D1 reset value errata.
• Added FEC max buffer size errata.
• Added eTPU debug errata.
• Added FEC EMRBR address errata.
03/2005
1.3
• Corrected previous errata with Table 9-8, Footnote #2.
• Added WAKEINT errata in Chapter 21.
• Added PAR_TSIZ0 errata.
• Added D[19:18]->D[20:19] errata.
• Added PSTCLK errata in Chapter 32.
07/2005
1.4
• Added pin F10 errata in Chapter 2 and 12.
• Added ERXER and ETXER direction errata in Chapter 2 and 12.
• Added default output pad drive strength errata.
• Added Table 7-3 footnote errata.
• Added SKHA parity errata
• Added UART external clock source, 16-bit divider errata.
08/2005
1.5
• Added FlexCAN errata in power management chapter.
12/2005
1.6
• Added PSTCLK errata in Chapter 2.
• Added multiple errata regarding the PLL unable to be stopped during stop
mode.
• Added MFD bit field errata.
• Added core watchdog reset errata.
• Added reset config override signal description errata in Chapter 9.
• Added chip select configuration entry errata.
• Added chip select signal description errata in Chapter 16.
• Added CSMRn[BAM] example errata.
• Added SDRAM address line note errata.
• Added DMA Timer MODE16 bit errata.
• Added MDHA & SKHA application examples errata.
• Added the SKMR[CTRM] bit field errata.
03/2006
1.7
• Added watchdog timer divide-by value errata.
07/2006