Errata for Revision 1.1
MCF5235 Reference Manual Errata, Rev. 2.2
Freescale Semiconductor
7
Section 18.3.4.1/Page 18-10 Add Note “Because the device has 24 external address lines, the maximum SDRAM
address size is 128 Mbits.”
Throughout Chapter 19
The maximum buffer size of the FEC is 2032 bytes. Replace all instances of 2047 with 2032.
R_BUF_SIZE is at bit position 10:4 in the EMRBR register. Therefore the maximum
setting is $7F0 which equals 2032.
Figure 19-24/Page 19-28
Change EMRBR register address to “ 0x1188” instead of “0x11B8”.
Section 21.3.2.6/Page 21-16 Remove reference to WAKINT in second paragraph
Figure 22-1/Page 22-2
Change value in divide by box to 4096 instead of 8192.
Table 24-3/Page 24-6
The MODE16 bit field description should read: “Selects the increment mode for the timer.
MODE16 = 1 is intended to exercise the upper bits of the 32-bit timer in diagnostic software
without requiring the timer to count through its entire dynamic range. When set, the
counter’s upper 16 bits mirror its lower 16 bits. All 32 bits of the counter are still compared
to the reference value.”
Figure 26-17/Page 26-18
Remove 16-bit divider blocks from both timer inputs, as it is not available when using an
external clock source.
Section 26.4.1.2.2/Page
26-19
Change equation to: Baudrate = f
extc
/(16 or 1), since the 16-bit divider is not available when
using an external clock source.
Section 28.4.1/Page 28-15 Swap steps 4 & 5 and change “...(without padding) in bits” to “...(without padding) in bytes”.
Section 28.4.2.1/Page 28-16 Swap steps 4 & 5.
Section 28.4.2.2/Page 28-16 Swap steps 4 & 5.
Section 28.4.2.3/Page 28-17 Swap steps 8 & 9.
Section 28.4.3/Page 28-18 Swap steps 8 & 9.
Section 28.4.4/Page 28-18 Swap steps 6 & 7.
Section 28.4.5/Page 28-18 Swap steps 7 & 8.
Figure 30-8/Page 30-7
Change SKMR[CTRM] bit field to straddle bits 11–8.
Table 30-2/Page 30-8
Change the first 4 SKMR bit fields bit numbers to 31–12, 11–8, 7, & 6–5.
Section 30.3.1/Page30-19
Remove last sentence of section, as this refers to internal logic only.
Section 30.4.1/Page 30-20 Swap steps 9 & 10.
Section 30.4.2/Page 30-20 Swap steps 9 & 10.
Swap steps 23 & 24.
Figure 30-7/Page 30-15
Replace entries with “Bytes 5-7 + Parity” with “Bytes 5-8” to reduce confusion. The parity is
included in the last bit of each byte, not the 8th byte.
Throughout Chapter 32
Replace CLKOUT with PSTCLK throughout.
Chapter 32
Add the following note to the beginning of the eTPU debug section: “eTPU debug
functionality is not available when the ColdFire processor is halted (STOP, DOZE, or
WAIT modes).”
Table 2. MCF5235RM Rev 1.1 Errata (continued)
Location
Description