Errata for Revision 2
MCF5235 Reference Manual Errata, Rev. 2.2
Freescale Semiconductor
3
Table 12-10/Page 12-22
In PAR_TSIZ1 field change CIM to CCM.
In PAR_TSIZ0 field change CIM to CCM.
Table 13-1/Page 13-3
Replace table with the one below to better illustrate the interrupt priority and level
assignments.
Table 13-2/Page 13-5
In footnote, remove mention of the SWIACK register, as it is not supported in the global
IACK space.
Table 13-3/Page 13-6
Added global IACK addresses for the L1IACK–L7IACK registers in the IPSBAR offset
column, 0xFE4–0xFFC.
Section 13.2.1.7/Page 13-18 Change last paragraph to: “In addition to the IACK registers within each interrupt controller,
there are global LnIACK registers. A read from one of the global LnIACK registers returns
the vector for the highest priority unmasked interrupt within a level for all interrupt
controllers. There is no global SWIACK register. However, reading the SWIACK register
from each interrupt controller returns the vector number of the highest priority unmasked
request within that controller.”
Section 14.4/Page 14-13
Remove last sentence in this section starting with “BCRn decrements...” since SAA bit is
not supported.
Section 14.4.4.1/Page 14-16 Change DREQ[32:0] to DREQ[3:0].
Table 1. MCF5235RM Rev 2 Errata (continued)
Location
Description
Interrupt
Level
ICR[IL]
Priority
ICR[IP]
Supported Interrupt
Sources
7
7
#8–63
6
5
4
— (Mid-point)
#7 (IRQ7)
3
#8–63
2
1
0
6
7–4
#8–63
— (Mid-point)
#6 (IRQ6)
3–0
#8–63
5
7–4
#8–63
— (Mid-point)
#5 (IRQ5)
3–0
#8–63
4
7–4
#8–63
— (Mid-point)
#4 (IRQ4)
3–0
#8–63
3
7–4
#8–63
— (Mid-point)
#3 (IRQ3)
3–0
#8–63
2
7–4
#8–63
— (Mid-point)
#2 (IRQ2)
3–0
#8–63
1
7–4
#8–63
— (Mid-point)
#1 (IRQ1)
3–0
#8–63