NXP Semiconductors MC9S12VRP64, Owner Reference Manual

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S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V8)
MC9S12VRP Family Reference Manual Rev. 1.3
132 NXP Semiconductors
Table 4-13. CPMUCOP Field Descriptions
Field Description
7
WCOP
Window COP Mode Bit — When set, a write to the CPMUARMCOP register must occur in the last 25% of the
selected period.A write during the first 75% of the selected period generates a COP reset.As long as all writes
occur during this window, $55 can be written as often as desired.Once $AA is written after the $55, the time-out
logic restarts and the user must wait until the next window before writing to CPMUARMCOP.
Table 4-14 shows
the duration of this window for the seven available COP rates.
0 Normal COP operation
1 Window COP operation
6
RSBCK
COP and RTI Stop in Active BDM Mode Bit
0 Allows the COP and RTI to keep running in Active BDM mode.
1 Stops the COP and RTI counters whenever the part is in Active BDM mode.
5
WRTMASK
Write Mask for WCOP and CR[2:0] Bit — This write-only bit serves as a mask for the WCOP and CR[2:0] bits
while writing the CPMUCOP register. It is intended for BDM writing the RSBCK without changing the content of
WCOP and CR[2:0].
0 Write of WCOP and CR[2:0] has an effect with this write of CPMUCOP
1 Write of WCOP and CR[2:0] has no effect with this write of CPMUCOP.
(Does not count for “write once”.)
2–0
CR[2:0]
COP Watchdog Timer Rate Select — These bits select the COP time-out rate (see Table 4-14 and Table 4-15 ).
Writing a nonzero value to CR[2:0] enables the COP counter and starts the time-out period.A COP counter
time-out causes a System Reset.This can be avoided by periodically (before time-out) initializing the COP
counter via the CPMUARMCOP register.
While all of the following four conditions are true the CR[2:0], WCOP bits are ignored and the COP operates at
highest time-out period (
2
24
cycles) in normal COP mode (Window COP mode disabled):
1) COP is enabled (CR[2:0] is not 000)
2) BDM mode active
3) RSBCK = 0
4) Operation in Special Mode
Table 4-14. COP Watchdog Rates if COPOSCSEL1=0.
(default out of reset)
CR2 CR1 CR0
COPCLK
Cycles to time-out
(COPCLK is either IRCCLK or
OSCCLK depending on the
COPOSCSEL0 bit)
0 0 0 COP disabled
0 0 1 2
14
0 1 0 2
16
0 1 1 2
18
1 0 0 2
20
1 0 1 2
22
1 1 0 2
23
1 1 1 2
24