DR
AFT
DR
AFT
DRAFT
DR
D
RAFT
DRAFT
DRA
FT DRAF
D
RAFT DRAFT DRAFT DRAFT DRAFT D
DRAFT
D
RAFT DRA
FT DRAFT DRAFT DRAFT DRA
LPC2917_19_1
© NXP B.V. 2007. All rights reserved.
Preliminary data sheet
Rev. 1.01 — 15 November 2007
49 of 68
NXP Semiconductors
LPC2917/19
ARM9 microcontroller with CAN and LIN
Table 27.
Branch clock overview
Legend:
"1" Indicates that the related register bit is tied off to logic HIGH, all writes are ignored
"0" Indicates that the related register bit is tied off to logic LOW, all writes are ignored
“+” Indicates that the related register bit is readable and writable
Branch Clock Name
Base Clock
Implemented Switch On/Off
Mechanism
WAKEUP
AUTO
RUN
CLK_SAFE
BASE_SAFE_CLK
0
0
1
CLK_SYS_CPU
BASE_SYS_CLK
+
+
1
CLK_SYS
BASE_SYS_CLK
+
+
1
CLK_SYS_PCR
BASE_SYS_CLK
+
+
1
CLK_SYS_FMC
BASE_SYS_CLK
+
+
+
CLK_SYS_RAM0
BASE_SYS_CLK
+
+
+
CLK_SYS_RAM1
BASE_SYS_CLK
+
+
+
CLK_SYS_SMC
BASE_SYS_CLK
+
+
+
CLK_SYS_GESS
BASE_SYS_CLK
+
+
+
CLK_SYS_VIC
BASE_SYS_CLK
+
+
+
CLK_SYS_PESS
BASE_SYS_CLK
+
+
+
CLK_SYS_GPIO0
BASE_SYS_CLK
+
+
+
CLK_SYS_GPIO1
BASE_SYS_CLK
+
+
+
CLK_SYS_GPIO2
BASE_SYS_CLK
+
+
+
CLK_SYS_GPIO3
BASE_SYS_CLK
+
+
+
CLK_SYS_IVNSS_A
BASE_SYS_CLK
+
+
+
CLK_SYS_MSCSS_A
BASE_SYS_CLK
+
+
+
CLK_SYS_CHCA
BASE_SYS_CLK
+
+
+
CLK_SYS_CHCB
BASE_SYS_CLK
+
+
+
CLK_PCR_SLOW
BASE_PCR_CLK
+
+
1
CLK_IVNSS_VPB
BASE_IVNSS_CLK
+
+
+
CLK_IVNSS_CANC0
BASE_IVNSS_CLK
+
+
+
CLK_IVNSS_CANC1
BASE_IVNSS_CLK
+
+
+
CLK_IVNSS_LIN0
BASE_IVNSS_CLK
+
+
+
CLK_IVNSS_LIN1
BASE_IVNSS_CLK
+
+
+
CLK_MSCSS_VPB
BASE_MSCSS_CLK
+
+
+
CLK_MSCSS_MTMR0
BASE_MSCSS_CLK
+
+
+
CLK_MSCSS_MTMR1
BASE_MSCSS_CLK
+
+
+
CLK_MSCSS_PWM0
BASE_MSCSS_CLK
+
+
+
CLK_MSCSS_PWM1
BASE_MSCSS_CLK
+
+
+
CLK_MSCSS_PWM2
BASE_MSCSS_CLK
+
+
+
CLK_MSCSS_PWM3
BASE_MSCSS_CLK
+
+
+
CLK_MSCSS_ADC1_VPB BASE_MSCSS_CLK
+
+
+
CLK_MSCSS_ADC2_VPB BASE_MSCSS_CLK
+
+
+
CLK_UART0
BASE_UART_CLK
+
+
+
CLK_UART1
BASE_UART_CLK
+
+
+