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LPC2917_19_1
© NXP B.V. 2007. All rights reserved.
Preliminary data sheet
Rev. 1.01 — 15 November 2007
36 of 68
NXP Semiconductors
LPC2917/19
ARM9 microcontroller with CAN and LIN
The ADC clock is limited to 4.5 MHz maximum frequency and should always be lower
than or equal to the system clock frequency. To meet this constraint or to select the
desired lower sampling frequency the clock generation unit provides a programmable
fractional system-clock divider dedicated to the ADC clock. Conversion rate is determined
by the ADC clock frequency divided by the number of resolution bits plus one. Accessing
ADC registers requires an enabled ADC clock, which is controllable via the clock
generation unit, see
Section 8.8.4
.
Each ADC has four start inputs. Note that start 0 and start 2 are captured in the system
clock domain while start 1 and start 3 are captured in the ADC domain. The start inputs
are connected at MSCSS level, see
Section 8.7.2.1
for details.
8.7.5.3
ADC pin description
The two ADC modules in the MSCSS have the pins described below. The ADCx input
pins are combined with other functions on the port pins of the LPC2917/19. The VREFN
and VREFP pins are common for both ADCs.
Table 20
shows the ADC pins.
Fig 9.
ADC block diagram
ADC
control
&
registers
ADC
control
&
registers
VPB
system
bus
update
Conversion data
Config data
IRQ
Start 0
Start 2
Start 1
Start 3
CLK_ADCx_VPB
(MSCSS SubSystem clock)
CLK_ADCx
(ADC clock)
(upto 4.5 MHz)
Analog
inputs
ADC1: 8
ADC2: 8
Sync_out
ADC
IRQ
3.3 V
Analog
to
Digital
convertor
Analog
mux
ADC domain
VPB SubSystem
domain
001aad331 **
Table 20.
Analog to digital converter pins
Symbol
Direction
Description
ADCn IN[7:0]
in
analog input for ADCn, channel 7 to channel 0 (n is 1 or 2)
ADCn_EXT_START
in
ADC external start-trigger input (n is 1 or 2)
VREFN
in
ADC LOW reference level
VREFP
in
ADC HIGH reference level