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NXP Semiconductors LPC2917, Preliminary Data Sheet, Page: 24 / 68

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NXP Semiconductors LPC2917 Preliminary Data Sheet Download Page 24

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LPC2917_19_1

© NXP B.V. 2007. All rights reserved.

Preliminary data sheet

Rev. 1.01 — 15 November 2007 

24 of 68

NXP Semiconductors

LPC2917/19

ARM9 microcontroller with CAN and LIN

•

CLK_SAFE see 

Section 7.2.2

8.4.2 Watchdog timer

8.4.2.1

Overview

The purpose of the watchdog timer is to reset the ARM9 processor within a reasonable 
amount of time if the processor enters an error state. The watchdog generates a system 
reset if the user program fails to trigger it correctly within a predetermined amount of time.

Key features:

•

Internal chip reset if not periodically triggered

•

Timer counter register runs on always-on safe clock

•

Optional interrupt generation on watchdog timeout

•

Debug mode with disabling of reset

•

Watchdog control register change-protected with key

•

Programmable 32-bit watchdog timer period with programmable 32-bit prescaler.

8.4.2.2

Description

The watchdog timer consists of a 32-bit counter with a 32-bit prescaler.

The watchdog should be programmed with a time-out value and then periodically 
restarted. When the watchdog times out it generates a reset through the RGU.

To generate watchdog interrupts in watchdog debug mode the interrupt has to be enabled 
via the interrupt enable register. A watchdog-overflow interrupt can be cleared by writing 
to the clear-interrupt register. 

Another way to prevent resets during debug mode is via the Pause feature of the 
Watchdog Timer. The watchdog is stalled when the ARM9 is in debug mode and the 
PAUSE_ENABLE bit in the Watchdog Timer Control register is set.

The Watchdog Reset output is fed to the Reset Generator Unit (RGU). The RGU contains 
a reset source register to identify the reset source when the device has gone through a 
reset. See 

Section 8.8.5

.

8.4.2.3

Pin description

The watchdog has no external pins.

8.4.2.4

Watchdog timer clock description

The Watchdog Timer is clocked by two different clocks; CLK_SYS_PESS and 
CLK_SAFE, see 

Section 7.2.2

. The register interface towards the system bus is clocked 

by CLK_SYS_PESS. The timer and prescale counters are clocked by CLK_SAFE which 
is always on.

8.4.3 Timer

8.4.3.1

Overview

The LPC2917/19 contains six identical timers: four in the peripheral subsystem and two in 
the Modulation and Sampling Control SubSystem (MSCSS) located at different peripheral 
base addresses. This section describes the four timers in the peripheral subsystem. Each 

Summary of Contents for LPC2917

Page 1: ...s of An ARM968E S processor with real time emulation support An AMBA multi layer Advanced High performance Bus AHB for interfacing to the on chip memory controllers Two DTL buses a universal NXP inter...

Page 2: ...ARM968E S is based on the ARMv5TE five stage pipeline architecture Typically in a three stage pipeline architecture while one instruction is being executed its successor is being decoded and a third...

Page 3: ...FO depths Three full duplex Q SPIs with four slave select lines 16 bits wide 8 locations deep Tx FIFO and Rx FIFO Four 32 bit timers each containing four capture and compare registers linked to I Os 3...

Page 4: ...with real time in circuit emulator Boundary scan test supported Dual power supply CPU operating voltage 1 8 V 5 I O operating voltage 2 7 V to 3 6 V inputs tolerant up to 5 5 V 144 pin LQFP package 4...

Page 5: ...Static Memory Controller SMC Embedded SRAM Memory 32 Kb SRAM Controller 0 Embedded FLASH Memory 512 768 Kb FLASH Memory Controller FMC Embedded SRAM Memory 16 Kb SRAM Controller 1 GLOBAL ACCEPTANCE FI...

Page 6: ...this section 6 2 2 LQFP144 pin assignment Fig 2 Pin configuration for SOT486 1 LQFP144 LPC2917FBD144 LPC2919FBD144 108 37 72 144 109 73 1 36 144PINS Table 3 LQFP144 pin assignment Symbol Pin Descript...

Page 7: ...ART PWM TRAP2 PWM3 MAT3 P1 26 30 GPIO 1 pin 26 PWM2 MAT0 PWM TRAP3 PWM3 MAT2 VDD IO 31 3 3 V power supply for I O P1 25 32 GPIO 1 pin 25 PWM1 MAT0 PWM3 MAT1 P1 24 33 GPIO 1 pin 24 PWM0 MAT0 PWM3 MAT0...

Page 8: ...pin 6 SPI1 SCS2 UART1 TxD EXTBUS A6 P2 6 69 GPIO 2 pin 6 TIMER1 MAT2 EXTINT2 EXTBUS D14 P1 5 70 GPIO 1 pin 5 SPI1 SCS1 PWM3 MAT5 EXTBUS A5 P1 4 71 GPIO 1 pin 4 SPI2 SCS2 PWM3 MAT4 EXTBUS A4 TRSTN 72...

Page 9: ...HIGH level selects boundary scan and flash programming pulled up internally NC 109 VREFP 110 HIGH reference for AD Converters VREFN 111 LOW reference for AD Converters P0 8 112 GPIO 0 pin 8 ADC1 IN0...

Page 10: ...uired because the clock rate when running at LP_OSC speed is too low for the external debugging environment 7 1 2 Reset strategy The LPC2917 19 contains a central module the Reset Generator Unit RGU i...

Page 11: ...an have different clock sources within the CGU The system clock for the CPU and AHB Multilayer Bus infrastructure has its own base clock This means most peripherals are clocked independently from the...

Page 12: ...M968E S m s s s s s s s s s External Static Memory Controller SMC Embedded SRAM Memory 32 Kb SRAM Controller 0 Embedded FLASH Memory 512 768 Kb FLASH Memory Controller FMC Embedded SRAM Memory 16 Kb S...

Page 13: ...more details of how to control the individual branch clocks Table 7 Base clock and branch clock overview Base clock Branch clock name Parts of the device clocked by this branch clock Remark BASE_SAFE...

Page 14: ...FMC interfaces to the embedded flash memory for two tasks Providing memory data transfer Memory configuration via triggering programming and erasing BASE_MSCSS_CLK CLK_MSCSS_VPB VPB side of the MSCSS...

Page 15: ...ns are read Flash can be read synchronously or asynchronously to the system clock In synchronous operation the flash goes into standby after returning the read data Started reads cannot be stopped and...

Page 16: ...tors of 8 kB each and up to 11 large sectors of 64 kB each The number of large sectors depends on the device type A sector must be erased before data can be written to it The flash memory also has sec...

Page 17: ...ess space Note that the index sector cannot be erased and that access to it has to be performed via code outside the flash 8 1 6 Flash bridge wait states To eliminate the delay associated with synchro...

Page 18: ...it states up to 32 for static RAM devices Programmable initial and subsequent burst read wait state for burst ROM devices Programmable write protection Programmable burst mode operation Programmable e...

Page 19: ...controller pins 8 2 4 External static memory controller clock description The External Static Memory Controller is clocked by CLK_SYS_SMC see Section 7 2 2 8 2 5 External memory timing diagrams A timi...

Page 20: ...iminary data sheet Rev 1 01 15 November 2007 20 of 68 NXP Semiconductors LPC2917 19 ARM9 microcontroller with CAN and LIN A timing diagram for writing to external memory is shown In Figure 5 The relat...

Page 21: ...ontroller with CAN and LIN Usage of the idle turn around time IDCY is demonstrated In Figure 6 Extra wait states are added between a read and a write cycle in the same external memory device Address p...

Page 22: ...ed on the chip 8 3 2 3 CFID pin description The CFID has no external pins 8 3 3 System Control Unit SCU 8 3 3 1 Overview The system control unit takes care of system related functions The key feature...

Page 23: ...ort pins of the LPC2917 19 Table 13 shows the pins connected to the event router and also the corresponding bit position in the event router registers and the default polarity 8 4 Peripheral subsystem...

Page 24: ...value and then periodically restarted When the watchdog times out it generates a reset through the RGU To generate watchdog interrupts in watchdog debug mode the interrupt has to be enabled via the i...

Page 25: ...tputs per timer corresponding to match registers with the following capabilities Set LOW on match Set HIGH on match Toggle on match Do nothing on match Pause input pin MSCSS timers only 8 4 3 2 Descri...

Page 26: ...e 16 byte receive and transmit FIFOs Registers conform to industry standard 550 Receiver FIFO trigger points at 1 byte 4 bytes 8 bytes and 14 bytes Built in baud rate generator 8 4 4 2 Description The...

Page 27: ...rate and prescale based on SPI source clock BASE_SPI_CLK independent of system clock Separate transmit and receive FIFO memory buffers 16 bits wide 32 locations deep Programmable choice of interface...

Page 28: ...ed with other functions on the port pins of the LPC2917 19 see Section 8 3 3 Table 16 shows the SPI pins x runs from 0 to 2 y runs from 0 to 3 1 Direction of SPIx SCS and SPIx SCK pins depends on mast...

Page 29: ...al port pin There are two registers to control I O direction and output level The inputs are synchronized to achieve stable read levels To generate an open drain output set the bit in the output regis...

Page 30: ...nly mode no acknowledge no active error flags Reception of own messages self reception request Full CAN mode for message reception 8 5 2 Global acceptance filter The global acceptance filter provides...

Page 31: ...d sampling control subsystem 8 7 1 Overview The Modulation and Sampling Control Subsystem MSCSS in the LPC2917 19 includes four Pulse Width Modulators PWMs three10 bit successive approximation Analog...

Page 32: ...nals Interrupt signals are generated on several events to closely interact with the CPU The ADCs can be used for any application needing accurate digitized data from analog sources To support applicat...

Page 33: ...nected to the start 3 inputs of the ADCs This signal is captured in the ADC clock domain The PWM_sync and trans_enable_in of PWM 0 are connected to the 4th match output of MSCSS timer 0 to start the P...

Page 34: ...d in Section 8 7 7 3 8 7 4 MSCSS clock description The MSCSS is clocked from a number of different sources 1 Timers c0 to c3 capture in 0 to capture in 3 m0 to m3 match out 0 to match out 3 2 ADCs st0...

Page 35: ...ers The key features of the ADC interface module are ADC1 and ADC2 Eight analog inputs time multiplexed measurement range up to 3 3 V External reference level inputs 400 ksamples per second at 10 bit...

Page 36: ...has four start inputs Note that start 0 and start 2 are captured in the system clock domain while start 1 and start 3 are captured in the ADC domain The start inputs are connected at MSCSS level see S...

Page 37: ...output signals Double edge features rising and falling edges programmed individually Optional interrupt generation on match each edge Different operation modes continuous or run once 16 bit PWM counte...

Page 38: ...l PWM consists of two counters a 16 bit prescale counter and a 16 bit PWM counter The position of the rising and falling edges of the PWM outputs can be programmed individually The prescale counter al...

Page 39: ...WM modules are clocked by CLK_MSCSS_PWMx x 0 3 see Section 7 2 2 Note that each PWM has its own CLK_MSCSS_PWMx branch clock for power management The frequency of all these clocks is identical to CLK_M...

Page 40: ...MTMRx x 0 1 see Section 7 2 2 Note that each timer has its own CLK_MSCSS_MTMRx branch clock for power management The frequency of all these clocks is identical to CLK_MSCSS_VPB since they are derived...

Page 41: ...see Section 7 2 2 CLK_SYS_PCRSS is derived from BASE_SYS_CLK which can be switched off in low power modes CLK_PCR_SLOW is derived from BASE_PCR_CLK and is always on in order to be able to wake up fro...

Page 42: ...ister write protection mechanism to prevent unintentional alteration of clocks Remark Any clock frequency adjustment has a direct impact on the timing of on board peripherals such as the UARTs SPI wat...

Page 43: ...cks a minimum of other logic in the device like the watchdog timer To prevent the device from losing its clock source LP_OSC cannot be put into power down The crystal oscillator can be used as source...

Page 44: ...be configured to get the required clock Multiple output generators can be connected to the same primary or secondary clock source and multiple secondary clock sources can be connected to the same PLL...

Page 45: ...ainst a currently selected clock going from active to inactive state Therefore an inactive clock may still be sent to the system under special circumstances although an interrupt can still be generate...

Page 46: ...ided by 2 4 8 or 16 depending on the value on the PSEL 1 0 input giving an output clock with a 50 duty cycle If a higher output frequency is needed the CCO clock can be sent directly to the output by...

Page 47: ...auses the output to go active Table 25 Reset output configuration Reset Output Reset Source parts of the device reset when activated POR_RST power on reset module LP_OSC is source for RGU_RST RGU_RST...

Page 48: ...f enabled clocks when a wake up event is received Status register is available to indicate if an input base clock can be safely switched off i e all branch clocks are disabled 8 8 6 2 Description The...

Page 49: ...BASE_SYS_CLK 1 CLK_SYS BASE_SYS_CLK 1 CLK_SYS_PCR BASE_SYS_CLK 1 CLK_SYS_FMC BASE_SYS_CLK CLK_SYS_RAM0 BASE_SYS_CLK CLK_SYS_RAM1 BASE_SYS_CLK CLK_SYS_SMC BASE_SYS_CLK CLK_SYS_GESS BASE_SYS_CLK CLK_SYS...

Page 50: ...ble routing of interrupt requests towards the ARM processor inputs IRQ and FIQ Fast identification of interrupt requests through vector Support for nesting of interrupt service routines 8 9 2 Descript...

Page 51: ...routines Software emulation of an interrupt requesting device including interrupts 8 9 3 VIC pin description The VIC module in the LPC2917 19 has no external pins 8 9 4 VIC clock description The VIC...

Page 52: ...charging a 100 pF capacitor via a 10 k series resistor 8 Machine model discharging a 200 pF capacitor via a 0 75 H series inductance and 10 resistor 9 112 mA per VDD IO or VSS IO should not be exceede...

Page 53: ...max clock speeds 1 1 2 5 mA MHz All clocks off 2 30 450 A I O supply VDD IO I O digital supply voltage 2 7 3 6 V Oscillator supply VDD OSC_PLL Oscillator and PLL supply voltage 1 71 1 80 1 89 V IDDD...

Page 54: ...age 0 VDD IO V VOH HIGH state output voltage IOH 4 mA VDD IO 0 4 V VOL LOW state output voltage IOL 4 mA 0 4 V CL Load capacitance 25 pF Analog to digital converter supply VVREFN Voltage on pin VREFN...

Page 55: ...e filter VDD CORE must be above Vtrip high for 2 s before reset is de asserted VDD CORE must be below Vtrip low for 11 s before internal reset is asserted 7 Not 5 V tolerant when pull up is on 8 For I...

Page 56: ...3 500 s PLL fi PLL PLL input frequency 10 25 MHz fo PLL PLL output frequency 10 160 MHz CCO direct mode 156 320 MHz Analog to digital converter fi ADC ADC input frequency 4 4 4 5 MHz fs max Maximum s...

Page 57: ...s parameter is not part of production testing or final testing hence only a typical value is stated 3 Oscillator start up time depends on the quality of the crystal For most crystals it takes about 10...

Page 58: ...L Lp Z y w v REFERENCES OUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 0 15 0 05 1 45 1 35 0 25 0 27 0 17 0 20 0 09 20 1 19 9 0 5 22 15 21 85 1 4 1 1 7 0 o o 0 08 0 2 0 08 1 DIMENSI...

Page 59: ...g may be necessary immediately after soldering to keep the temperature within the permissible limit 14 2 2 Manual soldering Apply the soldering iron 24 V or less to the lead s of the package either be...

Page 60: ...N10365 Surface mount reflow soldering description 14 3 2 Wave soldering Conventional single wave soldering is not recommended for surface mount devices SMDs or printed circuit boards with a high compo...

Page 61: ...le to the transport direction of the printed circuit board The footprint must incorporate solder thieves downstream and at the side corners During placement and before soldering the package must be fi...

Page 62: ...ersions with the heatsink on the bottom side the solder cannot penetrate between the printed circuit board and the heatsink On versions with the heatsink on the top side the solder might be deposited...

Page 63: ...ontroller with CAN and LIN 15 Abbreviations Table 35 Abbreviations list Abbreviation Description AHB Advanced High performance Bus BCL Buffer Control List BDL Buffer Descriptor List CISC Complex Instr...

Page 64: ...erved Preliminary data sheet Rev 1 01 15 November 2007 64 of 68 NXP Semiconductors LPC2917 19 ARM9 microcontroller with CAN and LIN 16 References 1 UM LPC2917 19 user manual 2 ARM ARM web site 3 ARM S...

Page 65: ...l rights reserved Preliminary data sheet Rev 1 01 15 November 2007 65 of 68 NXP Semiconductors LPC2917 19 ARM9 microcontroller with CAN and LIN 17 Revision history Table 36 Revision history Document I...

Page 66: ...to be suitable for use in medical military aircraft space or life support equipment nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to resu...

Page 67: ...tatic memory controller 18 8 2 1 Overview 18 8 2 2 Description 18 8 2 3 External static memory controller pin description 19 8 2 4 External static memory controller clock description 19 8 2 5 External...

Page 68: ...SS 40 8 7 7 1 Overview 40 8 7 7 2 Description 40 8 7 7 3 MSCSS timer pin description 40 8 7 7 4 MSCSS timer clock description 40 8 8 Power clock and reset control subsystem 40 8 8 1 Overview 40 8 8 2...

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