NXP Semiconductors K32 L2A Series, Reference Manual, Page: 412 / 1379

20.3.3 TCD structure
SADDR
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFF SMOD SSIZE DMOD DSIZE
SML
OE
DML
OE
MLOFF or NBYTES NBYTES
SLAST
DADDR
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CI
TER.E_LINK
CITER or
CITER.LINKCH
CITER DOFF
DLAST_SGA
BI
TER.E_LINK
BITER or
BITER.LINKCH
BITER
S
TAR
T
INT_MAJ
INT_HALF
D_REQ
E_SG
MAJOR.E_LINK
A
CTIVE
DONE
BWC
MAJOR.LINKCH
NBYTES
0000h
0004h
0008h
DMA_CR[EMLM] enabled
000Ch
0010h
0014h
0018h
001Ch
R
eser
ved
DMA_CR[EMLM] disabled
{
{
{
20.3.4 Reserved memory and bit fields
• Reading reserved bits in a register returns the value of zero.
• Writes to reserved bits in a register are ignored.
• Reading or writing a reserved memory location generates a bus error.
DMA memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4000_8000 Control Register (DMA0_CR) 32 R/W See section 20.3.5/418
4000_8004 Error Status Register (DMA0_ES) 32 R 0000_0000h 20.3.6/421
4000_800C Enable Request Register (DMA0_ERQ) 32 R/W 0000_0000h 20.3.7/423
4000_8014 Enable Error Interrupt Register (DMA0_EEI) 32 R/W 0000_0000h 20.3.8/425
4000_8018 Clear Enable Error Interrupt Register (DMA0_CEEI) 8
W
(always
reads 0)
00h 20.3.9/426
4000_8019 Set Enable Error Interrupt Register (DMA0_SEEI) 8
W
(always
reads 0)
00h 20.3.10/427
Table continues on the next page...
Memory map/register definition
K32 L2A Reference Manual, Rev. 2, 01/2020
412 NXP Semiconductors