NXP Semiconductors K32 L2A Series, Reference Manual, Page: 427 / 1379

DMAx_CEEI field descriptions (continued)
Field Description
CEEI Clear Enable Error Interrupt
Clears the corresponding bit in EEI
20.3.10 Set Enable Error Interrupt Register (DMAx_SEEI)
The SEEI provides a simple memory-mapped mechanism to set a given bit in the EEI to
enable the error interrupt for a given channel. The data value on a register write causes
the corresponding bit in the EEI to be set. Setting the SAEE bit provides a global set
function, forcing the entire EEI contents to be set. If the NOP bit is set, the command is
ignored. This allows you to write multiple-byte registers as a 32-bit word. Reads of this
register return all zeroes.
Address: 4000_8000h base + 19h offset = 4000_8019h
Bit 7 6 5 4 3 2 1 0
Read 0 0 0
Write NOP SAEE 0 SEEI
Reset 0 0 0 0 0 0 0 0
DMAx_SEEI field descriptions
Field Description
7
NOP
No Op enable
0 Normal operation
1 No operation, ignore the other bits in this register
6
SAEE
Sets All Enable Error Interrupts
0 Set only the EEI bit specified in the SEEI field.
1 Sets all bits in EEI
5–3
Reserved
This field is reserved.
SEEI Set Enable Error Interrupt
Sets the corresponding bit in EEI
Chapter 20 Enhanced Direct Memory Access (eDMA)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 427