NXP Semiconductors K32 L2A Series, Reference Manual, Page: 421 / 1379

DMAx_CR field descriptions (continued)
Field Description
NOTE: Do not use continuous link mode with a channel linking to itself if there is only one minor loop
iteration per service request, e.g., if the channel’s NBYTES value is the same as either the source
or destination size. The same data transfer profile can be achieved by simply increasing the
NBYTES value, which provides more efficient, faster processing.
0 A minor loop channel link made to itself goes through channel arbitration before being activated again.
1 A minor loop channel link made to itself does not go through channel arbitration before being activated
again. Upon minor loop completion, the channel activates again if that channel has a minor loop
channel link enabled and the link channel is itself. This effectively applies the minor loop offsets and
restarts the next minor loop.
5
HALT
Halt DMA Operations
0 Normal operation
1 Stall the start of any new channels. Executing channels are allowed to complete. Channel execution
resumes when this bit is cleared.
4
HOE
Halt On Error
0 Normal operation
1 Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit
is cleared.
3
Reserved
This field is reserved.
Reserved
2
ERCA
Enable Round Robin Channel Arbitration
0 Fixed priority arbitration is used for channel selection .
1 Round robin arbitration is used for channel selection .
1
EDBG
Enable Debug
0 When in debug mode, the DMA continues to operate.
1 When in debug mode, the DMA stalls the start of a new channel. Executing channels are allowed to
complete. Channel execution resumes when the system exits debug mode or the EDBG bit is cleared.
0
Reserved
This field is reserved.
Reserved
20.3.6 Error Status Register (DMAx_ES)
The ES provides information concerning the last recorded channel error. Channel errors
can be caused by:
• A configuration error, that is:
• An illegal setting in the transfer-control descriptor, or
• An illegal priority register setting in fixed-arbitration
• An error termination to a bus master read or write cycle
• A cancel transfer with error bit that will be set when a transfer is canceled via the
corresponding cancel transfer control bit
See Fault reporting and handling for more details.
Chapter 20 Enhanced Direct Memory Access (eDMA)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 421