NXP Semiconductors K32 L2A Series, Reference Manual, Page: 426 / 1379

DMAx_EEI field descriptions (continued)
Field Description
2
EEI2
Enable Error Interrupt 2
0 The error signal for corresponding channel does not generate an error interrupt
1 The assertion of the error signal for corresponding channel generates an error interrupt request
1
EEI1
Enable Error Interrupt 1
0 The error signal for corresponding channel does not generate an error interrupt
1 The assertion of the error signal for corresponding channel generates an error interrupt request
0
EEI0
Enable Error Interrupt 0
0 The error signal for corresponding channel does not generate an error interrupt
1 The assertion of the error signal for corresponding channel generates an error interrupt request
20.3.9 Clear Enable Error Interrupt Register (DMAx_CEEI)
The CEEI provides a simple memory-mapped mechanism to clear a given bit in the EEI
to disable the error interrupt for a given channel. The data value on a register write causes
the corresponding bit in the EEI to be cleared. Setting the CAEE bit provides a global
clear function, forcing the EEI contents to be cleared, disabling all DMA request inputs.
If the NOP bit is set, the command is ignored. This allows you to write multiple-byte
registers as a 32-bit word. Reads of this register return all zeroes.
Address: 4000_8000h base + 18h offset = 4000_8018h
Bit 7 6 5 4 3 2 1 0
Read 0 0 0
Write NOP CAEE 0 CEEI
Reset 0 0 0 0 0 0 0 0
DMAx_CEEI field descriptions
Field Description
7
NOP
No Op enable
0 Normal operation
1 No operation, ignore the other bits in this register
6
CAEE
Clear All Enable Error Interrupts
0 Clear only the EEI bit specified in the CEEI field
1 Clear all bits in EEI
5–3
Reserved
This field is reserved.
Table continues on the next page...
Memory map/register definition
K32 L2A Reference Manual, Rev. 2, 01/2020
426 NXP Semiconductors