NXP Semiconductors K32 L2A Series, Reference Manual, Page: 418 / 1379

DMA memory map (continued)
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4000_90DE
TCD Beginning Minor Loop Link, Major Loop Count
(Channel Linking Enabled)
(DMA0_TCD6_BITER_ELINKYES)
16 R/W Undefined 20.3.35/453
4000_90DE
TCD Beginning Minor Loop Link, Major Loop Count
(Channel Linking Disabled)
(DMA0_TCD6_BITER_ELINKNO)
16 R/W Undefined 20.3.36/454
4000_90E0 TCD Source Address (DMA0_TCD7_SADDR) 32 R/W Undefined 20.3.22/441
4000_90E4 TCD Signed Source Address Offset (DMA0_TCD7_SOFF) 16 R/W Undefined 20.3.23/441
4000_90E6 TCD Transfer Attributes (DMA0_TCD7_ATTR) 16 R/W Undefined 20.3.24/442
4000_90E8
TCD Minor Byte Count (Minor Loop Mapping Disabled)
(DMA0_TCD7_NBYTES_MLNO)
32 R/W Undefined 20.3.25/443
4000_90E8
TCD Signed Minor Loop Offset (Minor Loop Mapping
Enabled and Offset Disabled)
(DMA0_TCD7_NBYTES_MLOFFNO)
32 R/W Undefined 20.3.26/443
4000_90E8
TCD Signed Minor Loop Offset (Minor Loop Mapping and
Offset Enabled) (DMA0_TCD7_NBYTES_MLOFFYES)
32 R/W Undefined 20.3.27/445
4000_90EC
TCD Last Source Address Adjustment
(DMA0_TCD7_SLAST)
32 R/W Undefined 20.3.28/446
4000_90F0 TCD Destination Address (DMA0_TCD7_DADDR) 32 R/W Undefined 20.3.29/446
4000_90F4
TCD Signed Destination Address Offset
(DMA0_TCD7_DOFF)
16 R/W Undefined 20.3.30/447
4000_90F6
TCD Current Minor Loop Link, Major Loop Count (Channel
Linking Enabled) (DMA0_TCD7_CITER_ELINKYES)
16 R/W Undefined 20.3.31/447
4000_90F6 DMA0_TCD7_CITER_ELINKNO 16 R/W Undefined 20.3.32/449
4000_90F8
TCD Last Destination Address Adjustment/Scatter Gather
Address (DMA0_TCD7_DLASTSGA)
32 R/W Undefined 20.3.33/450
4000_90FC TCD Control and Status (DMA0_TCD7_CSR) 16 R/W Undefined 20.3.34/450
4000_90FE
TCD Beginning Minor Loop Link, Major Loop Count
(Channel Linking Enabled)
(DMA0_TCD7_BITER_ELINKYES)
16 R/W Undefined 20.3.35/453
4000_90FE
TCD Beginning Minor Loop Link, Major Loop Count
(Channel Linking Disabled)
(DMA0_TCD7_BITER_ELINKNO)
16 R/W Undefined 20.3.36/454
20.3.5 Control Register (DMAx_CR)
The CR defines the basic operating configuration of the DMA.
Arbitration can be configured to use either a fixed-priority or a round-robin scheme. For
fixed-priority arbitration, the highest priority channel requesting service is selected to
execute. The channel priority registers assign the priorities; see the DCHPRIn registers.
For round-robin arbitration, the channel priorities are ignored and channels are cycled
through (from high to low channel number) without regard to priority.
Memory map/register definition
K32 L2A Reference Manual, Rev. 2, 01/2020
418 NXP Semiconductors