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20.3.25 TCD Minor Byte Count (Minor Loop Mapping Disabled)
(DMAx_TCDn_NBYTES_MLNO)
This register, or one of the next two registers (TCD_NBYTES_MLOFFNO,
TCD_NBYTES_MLOFFYES), defines the number of bytes to transfer per request.
Which register to use depends on whether minor loop mapping is disabled, enabled but
not used for this channel, or enabled and used.
TCD word 2 is defined as follows if:
• Minor loop mapping is disabled (CR[EMLM] = 0)
If minor loop mapping is enabled, see the TCD_NBYTES_MLOFFNO and
TCD_NBYTES_MLOFFYES register descriptions for the definition of TCD word 2.
Address: 4000_8000h base + 1008h (32d × i), where i=0d to 7d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
R
W
Reset
x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*
* Notes:
x = Undefined at reset.
•
DMAx_TCDn_NBYTES_MLNO field descriptions
Field
Description
NBYTES
Minor Byte Transfer Count
Number of bytes to be transferred in each service request of the channel. As a channel activates, the
appropriate TCD contents load into the eDMA engine, and the appropriate reads and writes perform until
the minor byte transfer count has transferred. This is an indivisible operation and cannot be halted. It can,
however, be stalled by using the bandwidth control field, or via preemption. After the minor count is
exhausted, the SADDR and DADDR values are written back into the TCD memory, the major iteration
count is decremented and restored to the TCD memory. If the major iteration count is completed,
additional processing is performed.
NOTE: An NBYTES value of 0x0000_0000 is interpreted as a 4 GB transfer.
20.3.26 TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled
and Offset Disabled) (DMAx_TCDn_NBYTES_MLOFFNO)
One of three registers (this register, TCD_NBYTES_MLNO, or
TCD_NBYTES_MLOFFYES), defines the number of bytes to transfer per request.
Which register to use depends on whether minor loop mapping is disabled, enabled but
not used for this channel, or enabled and used.
Chapter 20 Enhanced Direct Memory Access (eDMA)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors
443
Summary of Contents for K32 L2A Series
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Page 122: ...Flash Memory Clock K32 L2A Reference Manual Rev 2 01 2020 122 NXP Semiconductors...
Page 158: ...Debug and security K32 L2A Reference Manual Rev 2 01 2020 158 NXP Semiconductors...
Page 174: ...Module Signal Description Tables K32 L2A Reference Manual Rev 2 01 2020 174 NXP Semiconductors...
Page 246: ...Application information K32 L2A Reference Manual Rev 2 01 2020 246 NXP Semiconductors...
Page 374: ...CMP Trigger Mode K32 L2A Reference Manual Rev 2 01 2020 374 NXP Semiconductors...
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