NXP Semiconductors K32 L2A Series, Reference Manual, Page: 446 / 1379

DMAx_TCDn_NBYTES_MLOFFYES field descriptions (continued)
Field Description
0 The minor loop offset is not applied to the DADDR
1 The minor loop offset is applied to the DADDR
29–10
MLOFF
If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or
destination address to form the next-state value after the minor loop completes.
NBYTES Minor Byte Transfer Count
Number of bytes to be transferred in each service request of the channel.
As a channel activates, the appropriate TCD contents load into the eDMA engine, and the appropriate
reads and writes perform until the minor byte transfer count has transferred. This is an indivisible operation
and cannot be halted. It can, however, be stalled by using the bandwidth control field, or via preemption.
After the minor count is exhausted, the SADDR and DADDR values are written back into the TCD
memory, the major iteration count is decremented and restored to the TCD memory. If the major iteration
count is completed, additional processing is performed.
20.3.28 TCD Last Source Address Adjustment (DMAx_TCDn_SLAST)
Address: 4000_8000h base + 100Ch (32d × i), where i=0d to 7d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
SLAST
W
Reset
x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*
* Notes:
x = Undefined at reset. •
DMAx_TCDn_SLAST field descriptions
Field Description
SLAST Last Source Address Adjustment
Adjustment value added to the source address at the completion of the major iteration count. This value
can be applied to restore the source address to the initial value, or adjust the address to reference the
next data structure.
This register uses two's complement notation; the overflow bit is discarded.
20.3.29 TCD Destination Address (DMAx_TCDn_DADDR)
Address: 4000_8000h base + 1010h (32d × i), where i=0d to 7d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
DADDR
W
Reset
x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*
* Notes:
x = Undefined at reset. •
Memory map/register definition
K32 L2A Reference Manual, Rev. 2, 01/2020
446 NXP Semiconductors