NXP Semiconductors K32 L2A Series, Reference Manual, Page: 425 / 1379

20.3.8 Enable Error Interrupt Register (DMAx_EEI)
The EEI register provides a bit map for the 8 channels to enable the error interrupt signal
for each channel. The state of any given channel’s error interrupt enable is directly
affected by writes to this register; it is also affected by writes to the SEEI and CEEI.
These registers are provided so that the error interrupt enable for a single channel can
easily be modified without the need to perform a read-modify-write sequence to the EEI
register.
The DMA error indicator and the error interrupt enable flag must be asserted before an
error interrupt request for a given channel is asserted to the interrupt controller.
Address: 4000_8000h base + 14h offset = 4000_8014h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
EEI7 EEI6 EEI5 EEI4 EEI3 EEI2 EEI1 EEI0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMAx_EEI field descriptions
Field Description
31–8
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
7
EEI7
Enable Error Interrupt 7
0 The error signal for corresponding channel does not generate an error interrupt
1 The assertion of the error signal for corresponding channel generates an error interrupt request
6
EEI6
Enable Error Interrupt 6
0 The error signal for corresponding channel does not generate an error interrupt
1 The assertion of the error signal for corresponding channel generates an error interrupt request
5
EEI5
Enable Error Interrupt 5
0 The error signal for corresponding channel does not generate an error interrupt
1 The assertion of the error signal for corresponding channel generates an error interrupt request
4
EEI4
Enable Error Interrupt 4
0 The error signal for corresponding channel does not generate an error interrupt
1 The assertion of the error signal for corresponding channel generates an error interrupt request
3
EEI3
Enable Error Interrupt 3
0 The error signal for corresponding channel does not generate an error interrupt
1 The assertion of the error signal for corresponding channel generates an error interrupt request
Table continues on the next page...
Chapter 20 Enhanced Direct Memory Access (eDMA)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 425