Fast Ethernet Controller (FEC)
Freescale Semiconductor
16-29
MCF51CN128 Reference Manual, Rev. 6
The 7-wire serial mode interface (RCR[MII_MODE] cleared) is generally referred to as AMD mode.
shows the 7-wire mode connections to the external transceiver.
16.5.7
FEC Frame Transmission
The Ethernet transmitter is designed to work with almost no intervention from software. After
ECR[ETHER_EN] is set and data appears in the transmit FIFO, the Ethernet MAC can transmit onto the
network. The Ethernet controller transmits bytes least significant bit (lsb) first.
When the transmit FIFO fills to the watermark (defined by TFWR), MAC transmit logic asserts
FEC_TXEN and starts transmitting the preamble (PA) sequence, the start frame delimiter (SFD), and then
the frame information from the FIFO. However, the controller defers the transmission if the network is
Table 16-32. MII Mode
Signal Description
EMAC pin
Transmit Clock
FEC_TXCLK
Transmit Enable
FEC_TXEN
Transmit Data
FEC_TXD[3:0]
Transmit Error
FEC_TXER
Collision
FEC_COL
Carrier Sense
FEC_CRS
Receive Clock
FEC_RXCLK
Receive Data Valid
FEC_RXDV
Receive Data
FEC_RXD[3:0]
Receive Error
FEC_RXER
Management Data Clock
FEC_MDC
Management Data
Input/Output
FEC_MDIO
Table 16-33. 7-Wire Mode Configuration
Signal description
EMAC Pin
Transmit Clock
FEC_
TXCLK
Transmit Enable
FEC_
TXEN
Transmit Data
FEC_
TXD[0]
Collision
FEC_
COL
Receive Clock
FEC_
RXCLK
Receive Data Valid
FEC_
RXDV
Receive Data
FEC_
RXD[0]
