NVIDIA Jetson TX2/TX2i OEM Product Design Guide
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
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Pin # Module Pin Name
Tegra Signal
Usage/Description
Usage on the Carrier
Board
Direction
Pin Type
D8
UART7_TX
UART7_TX
UART 7 Transmit
Output
CMOS
–
1.8V
Table 76. UART Interface Mapping
Module Pins (Tegra Functions)
I/O Block
Typical Usage
UART0 (UART1)
DEBUG
Debug
UART1 (UART3)
AO
Serial Port
UART2 (UART2)
UART
M.2 socket for external WLAN / BT
UART3 (UART4)
CONN
Jetson TX2
-
Misc. Available if not used for on-module WLAN
/ BT (selected by on-module multiplexor)
Jetson TX2i
-
Misc (no mux inv olved)
UART7 (UART7)
AO
2
nd
Debug/Misc.
Figure 41. UART Connections
Jetson TX2/TX2i
Tegra
– UART
UART3_TX
UART3_RX
UART3_RTS_N
UART3_CTS_N
AO
Serial Port,
etc.
(RAM_CODE1 St rap) UART 1_TX
UART 1_RX
UART 1_RTS#
UART 1_CTS#
(RAM_CODE1 St rap) RSVD
RSVD
UART 3_TX
UART 3_RX
UART 3_RTS#
UART 3_CTS#
UART 3_TX
UART 3_RX
UART 3_RTS#
UART 3_CTS#
UART 0_TX
UART 0_RX
(RAM_CODE0 St rap) UART 0_RTS#
UART 0_CTS#
UART 2_TX
UART 2_RX
UART 2_RTS#
UART 2_CTS#
UART1_TX
UART1_RX
UART1_RTS_N
UART1_CTS_N
DEBUG
UART2_TX
UART2_RX
UART2_RTS_N
UART2_CTS_N
UART
UART4_TX
UART4_RX
UART4_RTS_N
UART4_CTS_N
Used for
Debug, etc.
M.2 Conn.
(2
nd
WiFi/Bt)
B1 5
B1 6
H12
G12
H10
G9
D9
D10
E9
E10
G10
H9
G11
H11
A16
A15
CONN
Mux
WiFi / BT on
Jetson TX2
Misc.
UART7_TX
UART7_RX
D5
D8
Misc.
UART 7_TX_AP
UART 7_RX_AP
UART4_TX
UART4_RX
UART4_RTS_N
UART4_CTS_N
H10
G9
G10
H9
Misc.
Jet son TX2i
Jet son TX2
Note:
Care should be taken when using UART pins that are associated with Tegra straps. See Strapping Pins section for details.
Table 77. UART Signal Connections
Ball Name
Type
Termination
Description
UART[7,3:0]_TX
O
UART Transmit:
Connect to Peripheral
RXD
pin of device
UART[7,3:0]_RX
I
UART Receive:
Connect to Peripheral
TXD
pin of device
UART[3:0]_CTS#
I
UART Clear to Send:
Connect to Peripheral
RTS_N
pin of device
UART[3:0]_RTS#
O
UART Request to Send:
Connect to Peripheral
CTS
pin of device
