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NVIDIA Jetson TX2/TX2i OEM Product Design Guide

JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618

13.1 MPIO Pad Behavior w hen Associated Powe r Rail is Enabled .....................................................................................75

13.2 Internal Pull-ups for CZ Type Pins at Power-on.............................................................................................................75

13.3 Schm itt Trigger Usage .......................................................................................................................................................75

13.4 Pins Pulled/Driven High During Pow er -on......................................................................................................................75

13.5 Pad Drive Strength..............................................................................................................................................................76

14.0 UNUSED INT ERFA C E T ERMINATIONS .................................................................................................................................77

14.1 Unused MPIO Interfaces ....................................................................................................................................................77

14.2 Unused SFIO Interface Pins ..............................................................................................................................................77

15.0 DESIGN C HEC KLIST ................................................................................................................................................................78

16.0 A PPENDIX A : GENERAL LAYOUT GUIDELI NES ................................................................................................................86

16.1 Overview...............................................................................................................................................................................86

16.2 Via Guidelines .....................................................................................................................................................................86

16.3 Connecting Vias ..................................................................................................................................................................87

16.4 Trace Guidelines .................................................................................................................................................................87

17.0 A PPENDIX B: STAC K- UPS .....................................................................................................................................................89

17.1 Reference Design Stack -Ups ............................................................................................................................................89

18.0 A PPENDIX C : T RA NSMISSION LINE PRIMER ......................................................................................................................90

18.1 Background .........................................................................................................................................................................90

18.2 Physical Transm ission Line Types ..................................................................................................................................90

18.3 Driver Characteristics ........................................................................................................................................................91

18.4 Receiver Characteristics....................................................................................................................................................91

18.5 Transm ission Lines & Reference Planes ........................................................................................................................91

19.0 A PPENDIX D: DESIGN GUIDELINE GL OSSA RY .................................................................................................................94

20.0 A PPENDIX E: JETSON T X2/TX2I PIN DESC RI PTIONS .......................................................................................................95

Summary of Contents for JETSON TX2

Page 1: ...e the best performance from the common interfaces supported by the NVIDIA Jetson TX2 TX2i System on Module SOM This document provides detailed information on the capabilities of the hardw are module w...

Page 2: ...ing information and addedcaution note below f igure Debug Remov edexternal pull up on JTAG_GP0 JTAG_TRST_N Strapping Updated f igure table notes to remove mention of RAM_CODE 3 2 straps Pads Updated S...

Page 3: ...lengthguidelines to include device mode Updated minimum AC cap value Ethernet Updated Magnetics connections figure to show individual caps to GND on CT inputs of magnetics device HDMI DP Updated eDP D...

Page 4: ...ower on Type Detection Control 15 3 6 Power Voltage Monitoring 17 3 7 Deep Sleep SC7 18 3 8 Optional Auto Power On Support 19 4 0 GENERAL ROUTING GUIDELINES 21 5 0 USB PCIE SATA 23 5 1 USB 25 5 2 PCIe...

Page 5: ...nterfaces 77 14 2 Unused SFIO Interface Pins 77 15 0 DESIGN CHECKLIST 78 16 0 APPENDIX A GENERAL LAYOUT GUIDELINES 86 16 1 Overview 86 16 2 Via Guidelines 86 16 3 Connecting Vias 87 16 4 Trace Guideli...

Page 6: ...TX2i Supported Component List 1 2 Abbreviations and Definitions Table 2 lists abbreviations that may be used throughout this document and their definitions Table 2 Abbreviations and Definitions Abbrev...

Page 7: ...CLK I2S0_SDOUT 3 GND GND GND RSVD SPI0_CLK SPI0_CS0 GND GPIO20_AUD_INT 4 GND GND GND RSVD SPI0_MISO SPI0_MOSI DSPK_OUT_CLK DSPK_OUT_DAT 5 RSVD RSVD RSVD UART7_RX I2S3_SDIN I2S3_LRCLK I2S2_CLK I2S2_LRC...

Page 8: ...X1 GND DP0_TX0 39 USB1_D USB0_D GND PEX_RFU_TX DP1_TX0 GND PEX_RFU_RX DP0_TX0 40 GND USB0_D PEX2_TX PEX_RFU_TX GND PEX2_RX PEX_RFU_RX GND 41 PEX2_REFCLK GND PEX2_TX GND PEX1_TX PEX2_RX GND PEX1_RX 42...

Page 9: ...n Connected to PMIC EN0 whichhas internal 10K Pull upto VDD_5V0_SYS Also connected to Tegra POWER_ON pin through Diode with 100k pull upto VDD_1V8_AP near Tegra Input CMOS 5 0V see note 2 A47 RESET_IN...

Page 10: ...1 Supply Allocation Table 6 Internal Power Subsystem Allocation Power Rails Usage V Power Supply Source VDD_5V0_SYS Supplies various switchers load switches that power the various circuits peripheral...

Page 11: ...1V8 1V8_IO_VREG_EN RESET_OUT Main Carrier Board 1 8V Supply To Jetson TX2 RESET_OUT tokeep Tegra in Reset until 1 8V railValid Main 3 3V Power Good Routed to Power LED on Carrier board From Main 5V su...

Page 12: ...ush current during the rail transition OFF Sequence The associated NO_IOPOWER bit in the PMC APBDEV_PMC_NO_IOPOWER_0 register must be enabled before the I O Rail is powered OFF ON Sequence After an I...

Page 13: ...logic on the carrier board simulates edge triggered power on so the power button willfunction the same as for Jetson TX2 4 During run time ifany module I O rail is switchedOFF or ON the following seq...

Page 14: ...CARRIER_PWR_ON ramp down start to the module main 1 8V ramp down start Figure 6 Power Down Sequence Uncontrolled Power Removal Case CARRIER_PWR_ON VIN_PWR_BAD VDD_IN Carrier Board System Power Jetson...

Page 15: ...uF 0 05 Tol 100k 1 100k 1 G S D G S D G S D G S D G S D G S D 100 VDD_5V0_IO_SYS 47 VDD_3V3_SYS 36 VDD_1V8 47 VDD_3V3_SLP NTR4003 NT1G NTR4003 NT1G NTR4003 NT1G NTR4003 NT1G VDD_12V_SLP VDD_5V0_IO_SLP...

Page 16: ...t press of the pow er button w ill put the system in sleep mode softw are dependent if the system is aw ake w ake the system if in sleep mode or cause a force pow er off if the Pow er on button is hel...

Page 17: ...E VDD_5V0_SYS 1uF 1uF 1uF 100k VDD_1V8 INA_WIFI_THERM_WARN_L Figure 11 Power Monitor VDD_IN CPU DDR Sense Resistors GEN1_I2C_SDA GEN1_I2C_SCL INA3221AIRGVR Power Monitor VDD_IN_SENSE 0 02 1 3012 0 1uF...

Page 18: ...k 1 34k 1 49 9k 1 49 9k 1 110k 1 110k 1 COMP_SOC_THERM Tegra VCOMP_ALERT VOUT IN_POS IN_NEG VCC VEE VOUT IN_POS IN_NEG VCC VEE 100k 100k 1 8V Note The threshold for VDD_IN determined by the voltage di...

Page 19: ...irst pow ered instead of w aiting for a pow er button press For Jetson TX2 to enable this feature the CHARGER_PRSNT pin should be tied to GND For Jetson TX2i w hich uses a different PMIC the POWER_BTN...

Page 20: ...tson TX2i uses a different PMIC than Jetson TX2 The TX2i PMIC has a level sensitive on input so in order to pow er automatically w hen the main pow er is applied Auto Pow er On all that is required is...

Page 21: ...iption tables Table 12 Signal Type Codes Code Definition A Analog DIFF I O Bidirectional Differential Input Output DIFF IN Differential Input DIFF OUT Differential Output I O Bidirectional Input Outpu...

Page 22: ...m the module to the actual connector i e USB HDMI SD Card etc or device i e onboard USB device Display driver IC camera imager IC etc Trace Delay Flight Time Matching Signal flight time is the time it...

Page 23: ...mit PCIe IF 0 Output G42 USB_SS1_RX PEX_RX2P USB SS 1 Receive USB 3 0 Port 2 or PCIe IF 0 Lane 1 Input G43 USB_SS1_RX PEX_RX2N USB SS 1 Receive USB 3 0 Port 2 or PCIe 0 Lane 1 Input D42 USB_SS1_TX PEX...

Page 24: ...ns Module Pin Names PEX1 PEX_RFU PEX2 USB_SS1 PEX0 USB_SS0 see note 1 SATA Tegra Lanes Lane 0 Lane 1 Lane 3 Lane 2 Lane 4 Lane 5 Avail Outputs from the module Configs USB 3 0 PCIe SATA 1 0 1x1 1x4 1 P...

Page 25: ...n verified on the carrier board 8 See notes under the Backward Compatible mapping table related to color coding PCIe x2 x1 support lanereversal 5 1 USB Figure 15 USB 2 0 OTG USB 3 0 Host Connection Ex...

Page 26: ...ce the connector above would be the only Device capable connector in thesystem connected to Tegra USB0 must be used USB 2 0 Design Guidelines These requirements apply to the USB 2 0 controller PHY int...

Page 27: ...derived based on this characteristic See Note 1 Breakout Region Max trace length delay 11 73 mm ps Trace with minimum width and spacing Max PCB Trace Length Host Device 152 3 1014 50 8 334 mm ps Max W...

Page 28: ...aintain return path while its Xtalk suppression is limited Max of Vias PTH vias Micro Vias 4 Not limited as long as total channel loss meets IL spec Max Via Stub Length 0 4 mm long via stub requires r...

Page 29: ...USB 2 0 _D USB 2 0 _D DIFF I O 90 common mode chokes close to connector ESD Protection between choke connector on each line to GND USB Differential Data Pair Connect to USB connector Mini Card Socket...

Page 30: ..._TX USB_SS0_TX USB_SS0_RX USB_SS0_RX PEX0_REFCLK PEX0_REFCLK PEX_RFU_TX PEX_RFU_TX PEX_RFU_RX PEX_RFU_RX USB_SS1_TX USB_SS1_TX USB_SS1_RX USB_SS1_RX PEX2_TX PEX2_TX PEX2_RX PEX2_RX PEX0_TX PEX0_TX PEX...

Page 31: ...over antipads Not allowed AC Cap Value Min Max 0 075 0 2 uF Only required for TX pair when routed to connector Location max length to adjacent discontinuity 8 mm Discontinuity such as edge finger com...

Page 32: ...ins of PCIe connector or TX_ pin of PCIe device through AC cap according to supported configuration PEX2_REFCLK DIFF OUT Differential Reference Clock Output Connect to REFCLK_ pins of PCIe device conn...

Page 33: ...erential Configuration Device Organization 1 load Max Load per pin 0 5 pf Termination 100 On die termination Impedance Reference plane GND Trace Impedance Differential Pair Single Ended 95 45 55 15 Sp...

Page 34: ...been well verified with its 0 3pF capacitance Max distance from ESD Device to Connector 8 53 mm ps Recommended ESD layout Choke Preferred device Type TDK ACM2012D 900 2P Only if needed Place near con...

Page 35: ...acitor Differential Receive Data Pair Connect to SATA pins of SATA device connector through termination capacitor SATA_DEV_SLP O 1 8V to 3 3V level shifter SATA Device Sleep Connect through level shif...

Page 36: ...rmer Data 2 Bidir H48 GBE_MDI3 GbE Transformer Data 3 Bidir H47 GBE_MDI3 GbE Transformer Data 3 Bidir Figure 19 Ethernet Connections Jetson TX2 TX2i GBE_MDI0 GBE_MDI0 GBE_MDI1 GBE_MDI1 GBE_MDI2 GBE_MD...

Page 37: ...al Connections Module Pin Name Type Termination Description GBE_MDI 3 0 DIFF I O ESD device to GND per signal Gigabit Ethernet MDI IF Pairs Connect to Magnetics pins GBE_LINK_ACT O 681 series resistor...

Page 38: ...with 1 lane each DSI A 1x1 DSI B 1x1 or DSI C 1x1 DSI D 1x1 Two Links with 2 lane each DSI A 1x2 DSI B 1x2 or DSI C 1x2 DSI D 1x2 Four Links with 1 lane each DSI A 1x1 DSI B 1x1 DSI C 1x1 DSI D 1x1 Fo...

Page 39: ...I_C_D1_P DSI_C_D1_N DSI_D_CLK_P DSI_D_CLK_N DSI_D_D0_P DSI_D_D0_N DSI_D_D1_P DSI_D_D1_N Note If EMI ESD devices are necessary they must be tuned to minimize impact to signal quality which must meet th...

Page 40: ...wer traces areas or power supply components Note 1 If PWR 0 01uF decoupling cap required for return current 2 Up to 4 signal Vias can share a single GND return Via 3 If routing to device includes a fl...

Page 41: ...isplay Port 1 Aux or HDMI DDCSCL Bidir E38 DP1_TX0 HDMI_DP1_TXDN2 DisplayPort 1 Lane 0 or HDMI Lane 2 Output AC Coupled on carrier board E39 DP1_TX0 HDMI_DP1_TXDP2 DisplayPort 1 Lane 0 or HDMI Lane 2...

Page 42: ...ng preserve the polarity of the HPD signal from the display 2 Pull up downonly requiredfor DP not for eDP 3 If EMI devices are necessary they must be tuned to minimize the impact to signal quality whi...

Page 43: ...module to connector RBR HBR Stripline Microstrip HBR2 Stripline HBR2 Microstrip 5x 7x 165 1137 5 975 101 6 700 89 525 101 6 600 mm ps 175ps inch assumption for Stripline 150ps inch for Microstrip Trac...

Page 44: ...HBR HBR2 No requirement Voiding required HBR2 Voiding the plane directly under the pad 3 4 mils larger than the pad size is recommended Connector Voiding RBR HBR HBR2 No requirement Voiding required...

Page 45: ...x HDMI_CEC 10k B36 A33 B35 A35 B34 A34 B33 G37 D37 G36 D36 F38 C38 F37 C37 H39 E39 H36 E36 H35 E35 H38 E38 DPx_HPD DPx_AUX_CH DPx_AUX_CH HDMI_CEC DPx_TX2 DPx_TX2 DPx_TX1 DPx_TX1 DPx_TX0 DPx_TX DPx_TX3...

Page 46: ...quired See the RS section ofthe HDMI Interface Signal Routing Requirements tablefor details Table 43 HDMI Interface Signal Routing Requirements Parameter Requirement Units Notes Specification Max Freq...

Page 47: ...reference layers add one or two ground stitching vias It is recommended they be symmetrical to signal vias Via Topology 8 Y pattern is recommended 9 keep symmetry Xtalk suppression is the best by Y p...

Page 48: ...ts Top Bottom AC Cap Value 0 1 uF Max via distance from BGA 7 62 52 5 mm ps Location must be placed before pull down resistor The distance between the AC cap and the HDMI connector is not restricted P...

Page 49: ...MT area 1x dielectric height keepout distance Trace at Component Region Value 100 10 Location At component region Microstrip Trace entering the SMT pad One 45 Trace between components Uncoupled struct...

Page 50: ...ciated with one of the display output heads DPx_AUX_CH I OD From the module to Connector 10k PU to 3 3V level shifter 1 8k PU to 5V connector pin HDMI DDC Interface Clock and Data Connect DP1_AUX_CH t...

Page 51: ...LK CSI_D_CLK_N Camera CSI 3 Clock Input D25 CSI3_CLK CSI_D_CLK_P Camera CSI 3 Clock Input C25 CSI3_D0 CSI_D_D0_N Camera CSI 3 Data 0 Input C26 CSI3_D0 CSI_D_D0_P Camera CSI 3 Data 0 Input E23 CSI3_D1...

Page 52: ...TX2i 1k 1k VDD_1V8 120 120 Camera I2C Camera0 Clock Control Camera1 Clock Control Camera Strobe Flash CAM_AF_EN I2C_CAM_CLK I2C_CAM_DAT CAM0_MCLK GPIO0_CAM0_PWR GPIO2_CAM0_RST CAM1_MCLK GPIO1_CAM1_PW...

Page 53: ...E24 E23 D25 G21 F23 F22 H21 H20 G22 D21 C23 C22 E21 E20 D22 4 Lane B_CLK not used 2 Lane 2 Lane 2 Lane 2 Lane 4 Lane D_CLK not used 2 Lane 2 Lane 4 Lane F_CLK not used Note Any EMI ESD devices must be...

Page 54: ...Connections tables Camera Power Control signals or GPIOs 1 0 Connect to powerdown pins on camera s GPIO4_CAM_STROBE Camera Strobe Enable or GPIO 4 Connect to camera strobe circuit unless strobe contr...

Page 55: ...EDP3 SD Card power switch Enable Output CMOS 1 8V F20 SDCARD_WP GPIO_EDP1 SD Card Write Protect Input CMOS 1 8V B30 SDIO_CLK SDMMC3_CLK SDIO Clock SDIO Output CMOS 1 8V B29 SDIO_CMD SDMMC3_CMD SDIO Co...

Page 56: ...s Notes Max Frequency 3 3V Signaling DS HS 1 8V Signaling SDR12 SDR25 SDR50 SDR104 DDR50 25 12 5 50 25 25 12 5 50 25 100 50 208 104 50 50 MHz MB s See Note 1 Topology Point to point Reference plane GN...

Page 57: ...MD D 3 0 See note for EMI ESD SDIO SD Card Command Connect to CMD pin of device socket SDCARD_D 3 0 I O SDIO SD Card Data Connect to Data pins of device or socket SDCARD_CD I SD Card Card Detect Conne...

Page 58: ...C1_CLK I2S Audio Port 2 Left Right Clock Bidir CMOS 1 8V G6 I2S2_SDIN DMIC1_DAT I2S Audio Port 2 Data In Input CMOS 1 8V H6 I2S2_SDOUT DMIC2_CLK I2S Audio Port 2 Data Out Bidir CMOS 1 8V E6 I2S3_CLK D...

Page 59: ...r from DAPn_FS to GND is recommended ifTegra an I2S slave the edge_cntrlconfiguration 1 SDATA driven on positive edge ofSCLK The value ofthe capacitor should be chosen to provide a minimum of2ns hold...

Page 60: ...ogy Point to Point Reference plane GND Trace Impedance 45 50 20 Via proximity Signal via to GND return via 3 8 24 mm ps See Note Trace spacing Microstrip Stripline 2x 2x dielectric Max Trace Delay 128...

Page 61: ...SW4 CONN UART4_TX UART4_RX UART4_RTS_N UART4_CTS_N GPIO_PQ0 GPIO_PQ1 GPIO_PQ2 GPIO_PQ3 DMIC_HV MUX_SEL WIFI_EN WIFI_WAKE_AP BT2_WAKE_AP BT_EN AP2_WAKE_BT DAP6_SCLK DAP6_DOUT DAP6_DIN DAP6_FS H10 H9 G1...

Page 62: ...Requirement Units Notes Type Dual Band x2 Dipole Frequency Band s 2 4 5 0 GHz Impedance 50 Mating Connector Matching I PEX MHF or Hirose U FL Female See note 1 Note 1 Receptacles on Jetson TX2 are fro...

Page 63: ...a Bidir Open Drain 1 8V A34 DP1_AUX_CH DP_AUX_CH1_N Display Port 1 Aux or HDMI DDCSDA HDMI Type A Conn Bidir AC Coupled on Carrier Board eDP DP or Open Drain 1 8V 3 3V tolerant DDC I2C A35 DP1_AUX_CH...

Page 64: ...A20 C11 C10 C12 C13 GEN8_I2C_SCL GEN8_I2C_SDA VDD_1V8 1k 1k I2C2 I2C6 I2C5 I2C1 I2C3 I2C4 I2C9 I2C8 GEN7_I2C_SCL GEN7_I2C_SDA VDD_1V8 1k 1k Available for misc 1 8V I2C devices I2C7 Available for misc...

Page 65: ...tion for these pads For I2C interfaces that are pulled up to 3 3V enable the E_IO_HV option The E_IO_HV option is selected in thePinmux registers De bounce The tables below contain the allow able De b...

Page 66: ...AM The figure below show s the basic connections used Figure 37 Basic SPI Master Slave Connections Jetson TX2 TX2i Master SPIn_CSx SPIn_SCK SPIn_MOSI SPIn_MISO SPI Slave Device CS Chip Select CLK Cloc...

Page 67: ...points for initial boards Test Points Recommended Location One for each SPI signal line used Near the module Device pins 12 3 UART Jetson TX2 TX2i brings five UARTs out to the main connector One of th...

Page 68: ..._CTS UART3_TX UART3_RX UART3_RTS UART3_CTS UART0_TX UART0_RX RAM_CODE0 Strap UART0_RTS UART0_CTS UART2_TX UART2_RX UART2_RTS UART2_CTS UART1_TX UART1_RX UART1_RTS_N UART1_CTS_N DEBUG UART2_TX UART2_RX...

Page 69: ...sage on the Carrier Board Direction Pin Type C16 FAN_PWM GPIO_SEN6 Fan PWM Fan Output CMOS 1 8V B17 FAN_TACH UART5_TX Fan Tach Input CMOS 1 8V Figure 42 Fan Connection Example VDD_5V0_IO_SLP VDD_1V8 G...

Page 70: ...Signal RoutingRequirements Parameter Requirement Units Notes Max Data Rate Frequency 1 Mbps MHz Configuration Device Organization 1 load Reference plane GND Trace Impedance 50 15 Via proximity Signal...

Page 71: ...bugger documentation for JTAG PU PD recommendations 12 6 1 JTAG JTAG is not required but may be useful for new design bring up or for Boundary Scan Table 83 JTAG Pin Descriptions Pin Module Pin Name T...

Page 72: ...level shifter implemented 100k to supply on the non the module side of the device UART 0 Clear to Send Connect to RTS pin of serial device 12 6 3 Boundary Scan Test Mode To support Boundary Scan Test...

Page 73: ...See critical warning in Note 2 UART0_RTS UART1_RTS_N RAM_CODE0 100k PD 4 7K PU or none RSVD D8 UART7_TX BOOT_SELECT2 100k PD 4 7k PD Software reads value and determines Boot device to be configured a...

Page 74: ...e routed to a mux on Jetson TX2 and directed to either UART3_TX RTS or On module WLAN BT Since these pins are outputs and the mux is in the path Jetson TX2 UART3 pins will not affect the Boot Select 1...

Page 75: ...T CAN0_DIN Note The Pin Descriptions section of Jetson TX2 TX2i Data Sheetincludes thepin type information 13 3 Schmitt Trigger Usage The MPIO pins have an option to enable or disable Schmitt Trigger...

Page 76: ...RT0_TX Internal Pull up 100 CAM_VSYNC Internal Pull up 18 UART0_RX Internal Pull up 100 GPIO2_CAM0_RST Internal Pull up 18 WDT_TIME_OUT Driven High na Table 88 Module Pins Pulled Highon the Module Pri...

Page 77: ...sed can be left unconnected Table 90 Unused MPIO pins Pin Groups Module Pins Pin Groups Module Pins Pin Groups SLEEP SD_CARD SDIO TX2i only BATLOW AUDIO_x FORCE_RECOV I2S RESET_OUT DMIC WDT_TIME_OUT D...

Page 78: ...56K pull up to 3 3V PEX1_RST External 56K pull up to 3 3V PEX2_CLKREQ External 56K pull up to 3 3V PEX2_RST External 56K pull up to 3 3V PEX_WAKE External 56K pull up to 3 3V HDMI DP eDP DP0_HPD Inter...

Page 79: ...N External 10k pull up to 3 3V FORCE_RECOV Internal pull up to 1 8V SLEEP Internal pull up to 1 8V POWER_BTN Internal Pull Up to 1 8V near Tegra PMIC internal Pull up to 5 0V on other side of diodes m...

Page 80: ...or to 600 bead to GND 0 1uF capacitors DPx_TX2 499 1 resistor to 600 bead to GND 0 1uF capacitors DPx_TX1 499 1 resistor to 600 bead to GND 0 1uF capacitors DPx_TX0 499 1 resistor to 600 bead to GND 0...

Page 81: ...n main supply is stable VDD_5V0_IO_SYS Discharge implemented FET enabled by DISCHARGE w Source GND d 100 to VDD_5V0_IO_SYS VDD_3V3_SYS Discharge implemented FET enabled by DISCHARGE w Source GND d 47...

Page 82: ...sponding pins on connector or TX on device on the carrier board AC caps are provided for device TX pins those connected to the module RX if device is on the carrier board See Signal Terminations Refer...

Page 83: ...ble Signal Terminations DPx_AUX_CH connected to Aux Lane of panel connector See Signal Terminations DPx_HPD connected to HPD pin of panel connector Any EMI ESD devices used are suitable for highest fr...

Page 84: ...spective CAN device CAN_WAKE connected to Wake pin of CAN devices UART UARTx_TX connects to Peripheral RX pin of device UARTx_RX connects to Peripheral TX pin of device UARTx_CTS connects to Periphera...

Page 85: ...e NC any Clock lane not used DSI 3 0 _D 1 0 Leave NC any unused DSI Data lanes CSI CSI 5 0 _CK Leave NC any unused CSI Clock lanes CSI 5 0 _D 1 0 Leave NC any unused CSI Data lanes eDP DP DPx_TX 3 0 L...

Page 86: ...se of vias 16 2 1 Via Count and Trace Width As a general rule each ampere of current requires at least tw o micro vias 16 2 2 Via Placement If vias are not placed carefully they can severely degrade t...

Page 87: ...and the receiver on the module Signal trace requirements are determined by the driver characteristics source characteristics and signal frequency of the propagating signal 16 4 1 Layer Stack Up The n...

Page 88: ...low able propagation delay and impedance for the signal Higher frequency signals must be treated as transmission lines see Appendix C Transmission Line Primer to determine proper trace characteristics...

Page 89: ...tack Up Impact on Signal Quality Both layer count and layer order impact signal integrity Proper inter signal spacing must be achievable Via count for critical signals must be minimized Current commen...

Page 90: ...istances that lead to attenuation and distortion creating signal integrity issues Figure 50 Typical Transmission Line Circuit Transmission Line ZS Z0 ZL Load Source Transmission lines are used to tran...

Page 91: ...Characteristics Receiver characteristics are important to the integrity and detectability of the signal The follow ing points identify key receiver concepts and equations for optimum signal integrity...

Page 92: ...the second trace is proportional to 1 1 D H 2 The signals need to be properly spaced to minimize crosstalk Figure 54 Crosstalk on Reference Plane Reference plane selection Solid ground is preferred as...

Page 93: ...changes plane Try not to change the reference plane if possible When a reference plane sw itches to different pow er rail a stitching capacitor is required Figure 57 Figure 57 Switching Reference Pla...

Page 94: ...height which is distance from trace to reference layers Pair to pair spacing Spacing between differential traces Breakout spacing Possible exception toboardtrace spacing where different spacing rules...

Page 95: ...k Bidir Open Drain 3 3V A22 GPIO_EXP1_INT GPIO_MDM7 GPIO Expander 1 Interrupt or GPIO GPIO Expander Input CMOS 1 8V A23 GPIO_EXP0_INT GPIO_MDM1 GPIO expander 0 Interrupt or GPIO Input CMOS 1 8V A24 LC...

Page 96: ...by The module drives this signal low when it is inthe standby power state System Output CMOS 1 8V B8 VIN_PWR_BAD VDD_IN Power Bad Carrier board indication to the module that the VDD_IN power is not va...

Page 97: ...ON pin through Diode with 100k pull upto VDD_1V8_APnear Tegra System Input CMOS 5 0V see note 3 C1 VDD_IN Main power Supplies PMIC external supplies Main DC input Input 5 5V 19 6V TX2 9 0V 19 0V TX2i...

Page 98: ...Camera Flash Enable or GPIO Output CMOS 1 8V D8 UART7_TX UART7_TX UART 7 Transmit Not Assigned Output CMOS 1 8V D9 UART1_TX UART3_TX UART 1 Transmit Serial Port Header Output CMOS 1 8V D10 UART1_RX UA...

Page 99: ...eader Output CMOS 1 8V E10 UART1_CTS UART3_CTS UART 1 Clear to Send Input CMOS 1 8V E11 RSVD Not used E12 RSVD Not used E13 RSVD Not used E14 SPI1_CS0 GPIO_CAM7 SPI 1 Chip Select 0 Expansion Header Bi...

Page 100: ...ata 3 Bidir CMOS 3 3 1 8V F19 SDCARD_D2 SDMMC1_DAT2 SD Card or SDIO Data 2 Bidir CMOS 3 3 1 8V F20 SDCARD_WP GPIO_EDP1 SD Card Write Protect Input CMOS 1 8V F21 GND GND GND GND F22 CSI4_D0 CSI_E_D0_N...

Page 101: ...5 CSI2_CLK CSI_C_CLK_P Camera CSI 2 Clock Input G26 GND GND GND GND G27 CSI0_CLK CSI_A_CLK_N Camera CSI 0 Clock Camera Connector Input MIPI D PHY G28 CSI0_CLK CSI_A_CLK_P Camera CSI 0 Clock Input G29...

Page 102: ...r Input MIPI D PHY H27 CSI0_D1 CSI_A_D1_P Camera CSI 0 Data 1 Input H28 GND GND GND GND H29 DSI2_D1 DSI_C_D1_P Display DSI 2 Data 1 Display Connector Output MIPI D PHY H30 DSI2_D1 DSI_C_D1_N Display D...

Page 103: ...eliability of the NVIDIA product and may result in additional or different conditions and or requirements beyond those containedin this specification NVIDIA does not accept any liability relatedto any...

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