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ISD3900

Publication Release Date: Dec 10, 2013

- 16 -

Revision 1.5

Analog outputs consist of:



AUXOUT is a single-ended voltage output



AUDOUT  can  be  configured  as  a  single-ended  voltage  output  or  a  single-ended  current
output.    When  configured  as  a  voltage  output,  AUDOUT  is  exactly  the  same  as  the
AUXOUT.



BTL (bridge-tied-load) is a differential voltage output, which shares the same two pins of
PWM (SPK+/SPK-). Signal source of BTL could be either from AUD_MUX or AUX_MUX.

o

Besides BTL, SPK+ and/or SPK- can also be configured individually:



SPK+ can switch to AUDOUT or AUXOUT



SPK- can switch to AUDOUT or AUXOUT

The  analog  path  consists  of  the  following  blocks:  AUXIN,  ANAIN  (or  MICIN),  SUM1,  ADC_MUX
(SUM1  and  ADC_MUX  are  ineffective  when  MICIN  is  selected),  SUM2,  SUM2_MUX,  AUD_MUX,
AUX_MUX, SPK+_MUX, and SPK-_MUX.  The summation blocks, SUM1 and SUM2, are able to mix
two signals together.  SUM1 mixes the two analog inputs (AUXIN and ANAIN) for input into the digital
signal path.  SUM2 mixes the analog input (AUXIN, or ANAIN, or AUXIN plus ANAIN) with the digital
signal  path  output.    ADC_MUX  provides  input  selection  into  the  ADC.    AUD_MUX  and  AUX_MUX
provide input selection into the AUDOUT and AUXOUT blocks.  SPK+_MUX and SPK-_MUX provide
input selection  into  the  SPK+  and  SPK-  blocks.   The  configuration  registers,  CFG5-CFG9  &  CFG18,
control the active path features, allow individual power control of each block and enable the muting of
certain path inputs.  The details of the path configuration registers are described in Section 12.3.

7.1.1

ANAIN & MICIN Analog Input

Single-ended ANAIN Input

ANAIN

ANAOUT

ANAIN

1V

pp

Vin

coup

C

in

R

f

R

Figure 7-3 ANAIN Input Amplifier

The ANAIN input amplifier is designed to allow a variable gain set via two external resistors. The goal

of gain selection is to produce a

pp

V

1

signal into the ISD3900 audio path. Voltage gain is:

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Summary of Contents for ISD3900

Page 1: ...ISD3900 Publication Release Date Dec 10 2013 1 Revision 1 5 ISD3900 Multi Message Record Playback Devices with Digital Audio Interface ...

Page 2: ...Voice Prompts 24 8 2 2 Voice Macros 24 8 2 3 User Data 25 8 2 4 Reserved Sectors 25 8 2 5 Message Recordings 25 8 3 MEMORY AND MESSAGE HEADERS 26 8 3 1 Memory Header 26 8 3 2 Message Header 27 8 4 DIGITAL ACCESS OF MEMORY 28 8 5 DEVICE ERASE COMMANDS 28 8 6 MEMORY CONTENTS PROTECTION 28 9 I 2 S INTERFACE 29 10 CLOCK GENERATION 30 10 1 EXTERNAL CRYSTAL OSCILLATOR 31 10 2 I2 S CLOCK USAGE 33 10 3 IN...

Page 3: ...DIGITAL MEMORY COMMANDS 75 13 3 1 Digital Read 75 13 3 2 Digital Write 75 13 3 3 Erase Memory 76 13 3 4 Chip Erase 77 13 4 DEVICE CONFIGURATION COMMANDS 77 13 4 1 PWR_UP Power up 77 13 4 2 PWR_DN Power Down 78 13 4 3 SET_CLK_CFG Set Clock Configuration Register 78 13 4 4 RD_CLK_CFG Read Clock Configuration Register 79 13 4 5 WR_CFG_REG Write Configuration Register 79 13 4 6 RD_CFG_REG Read Configu...

Page 4: ...comes MIC MIC in conjunction with an automatic gain control AGC circuit configured by SPI command Analog outputs are available in three forms 1 AUXOUT is a single ended voltage output 2 AUDOUT can be configured as either a single ended voltage output or a single ended current output 3 BTL bridge tied load is a differential voltage output 2 FEATURES External Memory support winbond s 25X and 25Q Spi...

Page 5: ...g input with 2 bit gain control configured by SPI command o ANAIN ANAOUT Analog input with the gain set by two external resistors from ANAOUT to ANAIN or Microphone differential input ANAIN ANAOUT becomes MIC MIC o Digital AGC Automatic gain control of digitized data from the analog input Outputs o PWM Class D speaker driver to direct drive an 8Ω speaker or buzzer o AUDOUT configurable as a curren...

Page 6: ...sion De Compression Flash Memory Controller I2S Interface SPI Interface Memory Management and Command Interpreter SCK SDI WS SCLK SSB MISO MOSI INTB RDY BSYB AUDOUT AUXOUT SPK SPK SUM1 SUM2 ADC_MUX SDO SUM2_MUX AUD_MUX AUX_MUX GPIO Controller GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 A G C ANAIN ANAOUT Av 0 3 6 9dB AUXIN SPK _MUX SPK _MUX CLK CSB DI DO Figure 3 1 ISD3900 Block Diagram ANAIN ...

Page 7: ...ssion De Compression Flash Memory Controller I2S Interface SPI Interface Memory Management and Command Interpreter SCK SDI WS SCLK SSB MISO MOSI INTB RDY BSYB AUDOUT AUXOUT SPK SPK SUM2 SDO SUM2_MUX AUD_MUX AUX_MUX GPIO Controller GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 A G C MIC MIC Av 0 3 6 9dB AUXIN SPK _MUX SPK _MUX CLK CSB DI DO Figure 3 2 ISD3900 Block Diagram MICIN Selected ...

Page 8: ...44 43 42 41 40 39 38 37 36 35 34 47 46 45 48 VSSD NC VCCD VREG I2 S_SDO GPIO4 I2 S_WS GPIO5 I2 S_SCK GPIO6 I2 S_SDI GPIO7 DI CSB NC V CCD _PWM NC NC SPK V SSD _PWM SPK V CCD _PWM MOSI SSB SCLK MISO NC INTB DO CLK RDY BSYB RESET XTALOUT XTALIN GPIO3 NC GPIO2 GPIO1 NC NC NC NC AUDOUT AUXOUT V CCA V SSA ANAOUT MIC ANAIN MIC AUXIN NC GPIO0 Figure 4 1 ISD3900 48 Lead LQFP Pin Configuration ...

Page 9: ...or WS output in master mode If I2S is not used this pin should be grounded Or can be configured as a GPIO pin 7 I 2 S_SDO GPIO4 O Serial Data Output of the I 2 S Interface If I2S is not used this pin should be left unconnected Or can be configured as a GPIO pin 8 NC This pin should be left unconnected 9 NC This pin should be left unconnected 10 VSSD I Digital Ground 11 VCCD I Digital power supply ...

Page 10: ...put Or can independently switch to AUDOUT or AUXOUT 21 VCCD_PWM I Digital Power for the PWM Driver 22 NC This pin should be left unconnected 23 NC This pin should be left unconnected 24 NC This pin should be left unconnected 25 INTB O Active low interrupt request pin This pin is an open drain output 26 RDY BSYB O An output pin to report the status of data transfer on the SPI interface High indicat...

Page 11: ...e internal registers via SPI command If AUDOUT is not used this pin should be left unconnected 42 AUXOUT O Aux Out This pin is an analog voltage output If AUXOUT is not used this pin should be left unconnected 43 VCCA I Analog power supply pin 44 VSSA I Analog ground pin 45 ANAOUT MIC O Variable gain analog output with the gain set by feedback resistance to ANAIN Or can be configured as MIC which ...

Page 12: ...LK MISO MOSI X C7 C6 C5 X C4 C3 C2 C1 C0 S7 S6 S5 S4 S3 S2 S1 S0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Z X Figure 6 1 SPI Data Transaction A transaction begins with sending a command byte C7 C0 with the most significant bit MSB C7 sent in first During the byte transmission the status S7 S0 of the device is sent out via the MISO pin After the byte transmission depending upon the command s...

Page 13: ...tus register will be set to zero and be reported via the MISO pin so the host can take the necessary actions i e terminate SPI transmission and re transmit the data when the RDY BSYB pin returns to high For commands i e DIG_READ SPI_PCM_READ and SPI_RCV_ENC that read data from ISD3900 MISO is used to read the data therefore the host must monitor the status via the RDY BSYB pin and take the necessa...

Page 14: ... 5 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 SSB SCLK MISO MOSI X C7 C6 C5 X C4 C3 C2 C1 C0 PD RDY INT FULL X VG BSY BUF FUL CMD BSY PD RDY INT FULL X VG BSY BUF FUL CMD BSY D7 D6 D5 D4 D3 D2 D1 D0 Z X RDY BSYB B R T 1 0 INT Figure 6 3 SPI Transaction Ignoring RDY BSYB ...

Page 15: ...UM2 ADC_MUX SUM2_MUX AUD_MUX AUX_MUX A G C ANAIN ANAOUT Av 0 3 6 9dB AUXIN SPK _MUX SPK _MUX Figure 7 1 Analog Signal Path ANAIN Selected Analog inputs consist of variable gain input amplifiers AUXIN can be configured by SPI command ANAIN is determined by a selection of external resistors ANAIN can also be configured as MICIN ANAIN ANAOUT becomes MIC MIC which provides a microphone differential in...

Page 16: ...M1 and SUM2 are able to mix two signals together SUM1 mixes the two analog inputs AUXIN and ANAIN for input into the digital signal path SUM2 mixes the analog input AUXIN or ANAIN or AUXIN plus ANAIN with the digital signal path output ADC_MUX provides input selection into the ADC AUD_MUX and AUX_MUX provide input selection into the AUDOUT and AUXOUT blocks SPK _MUX and SPK _MUX provide input sele...

Page 17: ...ut Figure 7 4 Differential MIC Input Amplifier The ISD3900 allows the use of pins ANAIN and ANAOUT as differential MIC inputs In this mode the ANAIN and ANAOUT pins become MIC and MIC and allow a differential input to be applied to the ADC This configuration is designed to be used in conjunction with the AGC to amplify microphone signals while achieving good common mode rejection of supply noise N...

Page 18: ...in frequency to pass through The relationship repeated here is coup in pass C R f 2 1 in R is the input impedance of the AUXIN amplifier and is dependent upon the gain setting as shown in Table 7 1 below Table 7 1 Gain Setting Vs Rin Setting Gain dB Gain Rin kOhms 00 0 1 00 40 0 01 3 1 41 33 2 10 6 2 00 26 7 11 9 2 82 21 0 The minimum value of in R is approximately 20kOhms so a coup C of 1µF will ...

Page 19: ...onfigured as a voltage output AUDOUT is exactly the same as the AUXOUT When configured as a current output it uses a transistor to drive the speaker Please note that the signal coming out of AUD_MUX is always voltage regardless configured as a voltage or current output if configured as a current output the AUDOUT block that follows the AUD_MUX converts the voltage signal to current signal AUDOUT D...

Page 20: ... Method Can direct drive but an external amplifier is required to reach adequate volume level Need an external amplifier Direct drive Driving Ability High depends on the external amplifier High depends on the external amplifier 360 mW Quality Typical 80dB with good noise rejection Typical 80dB Typical 60dB Cost Extra cost of the external amplifier Extra cost of the external amplifier No extra cost...

Page 21: ... into the signal path comes either from the ADC path or the I 2 S digital audio interface Audio at Fsub is up sampled and can be mixed with the input and level adjusted via VOLA VOLB and VOLC before going out on the DAC I 2 S or PWM driver paths The FIFO synchronizes audio sources at the sub sampled bandwidth One input and one output can be active at a time The possible combinations are SPI_IN COM...

Page 22: ...The Recording Memory Pointer RMP divides the ISD3900 memory address space into two blocks Reserved Memory and Recording Memory The RMP is a two byte address pointer pointing to a 4kByte memory sector which is the first sector available to users for recording messages Memory between address zero and the RMP pointer is considered the Reserved Memory for pre recorded audio Voice Prompts pre programme...

Page 23: ...that can be played back using the PLAY_VP SPI command or Voice Macros 2 Voice Macros A powerful voice script allowing users to create custom macros to play Voice Prompts play message recordings insert silence and configure the device Voice Macros are executed with a single SPI command 3 User Data Memory sectors defined and allocated by the users for use in other applications 4 Reserved Sectors Mem...

Page 24: ...y message recordings insert silence change the master sample clock power down the device and configure the signal path including gain and volume control Voice Macros are executed using a single SPI command and are accessed using the same index structure as Voice Prompts This means that a Voice Macro or Voice Prompt can be updated on the ISD3900 without the need to update code on the host micro con...

Page 25: ... Message to play erase the entire message or re record a brand new message The Re recordable Message a 4kByte memory sector contains message recordings and a sector address pointer see Section 8 3 for details pointing to the message sector located in Recording Memory Unlike the Empty Message where no message has been recorded the users can play back a complete message by issuing a SPI play command...

Page 26: ...g the memory protection scheme the RMP and PMP pointers and the index table including POI PU and other Voice Macros defined by the users The Message Header located in both Reserved Sectors and Recording Memory stores the information for the device to determine what memory is available for recording and where the subsequent messages are stored 8 3 1 Memory Header Table 8 1Memory Header Initial Byte...

Page 27: ...d below also see Section 8 6 for details Table 8 2 The first byte of the Memory Header Memory Header Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 1 1 0 0 1 RP WP CEP 8 3 2 Message Header Table 8 3 Message Header Message Header Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 BOM EOM RSVD The ISD3900 adopts a sector based message management scheme that treats each 4kByte sector as a mes...

Page 28: ...lows the users to protect external memory for an address range from the beginning of memory to this sector where PMP is pointed The type of protection is set by three bits in the memory header byte The CEP Chip Erase Protect bit set to zero enables chip erase protection This prevents a mass erase function allowing the device to be configured as a write once part With the CEP bit set to one even wi...

Page 29: ...left right or both channels It is also capable of feeding through a stereo signal and mixing a playback operation into the signal In slave mode to synchronize data transfer the ISD3900 must derive its master clock from the I 2 S SCK or be operating from a synchronous external clock source I 2 S is for high bandwidth audio input output High bandwidth audio input comes either from the ADC path or th...

Page 30: ...oop PLL to generate the internal master clock MCLK of the ISD3900 IIS_SCK XTAL_CLK M U X SEL_CLK_INP 1 0 MCLK PLL_REF_CLK PLL_OUT_CLK OSC_CLK M N PFD CHARGE PUMP LOOP FILTER VCO 2 FOSC Figure 10 1 PLL Clock Generation on ISD3900 The goal of clock generation is to generate a master clock rate MCLK at 512x the master sample rate Fs A table of supported master clock and sample rates is shown below Th...

Page 31: ...2 44 1 48 10 1 EXTERNAL CRYSTAL OSCILLATOR The external circuit for attaching a quartz crystal or ceramic resonator is shown in Figure 10 2 In this circuit Rf is several MΩ and is used to DC bias the internal amplifier R1 C1 and C2 are chosen so as not to overdrive the crystal and to suppress oscillation at higher crystal harmonics XTAL_IN XTAL_OUT C1 C2 R1 Rf XTAL Figure 10 2 Crystal Oscillator S...

Page 32: ... 44 1 16 9344 3 8 44 1 1 536 1 32 48 3 072 2 32 48 4 608 3 32 48 6 144 2 16 48 9 216 3 16 48 12 288 2 8 48 18 432 3 8 48 In addition to the above crystals to achieve standard audio sampling rates other frequencies could be used that would produce different sample rates For instance if the user wishes to use the standard USB clock rates of 6 or 12MHz the following master sample rates could be achie...

Page 33: ... 3 INTERNAL OSCILLATOR The ISD3900 also provides an internal oscillator For reference the internal oscillator uses an internal resistor or an external resistor If the device is configured to use internal oscillator with external resistor then the resistor should be connected between XTALIN pin and GND The internal oscillator with external resistor has an accuracy of 5 and gives a master sample rat...

Page 34: ... 0 and VM 1 are reserved for POI and PU initialization routines If no reserved memory exists or if the vectors VM 0 or VM 1 are not set then a default routine is executed The default sequence for POI is to power down the ISD3900 The default PU sequence is to select a clock configuration of internal oscillator with PLL active for Fs 32kHz POI VP Sector Exist Send PU to Memory Send PD to memory VM 0...

Page 35: ...us OK Table 13 2 Proper Path Set yes yes no no Execute IDLE Generate CMD_ERR Interrupt Assert CMD_BSY Pending Proper Index Address no Execute Fill FIFO yes Stop Command Reach End no Generate CMD_FIN Interrupt IDLE no yes yes In Power up State yes no Figure 11 2 Record Playback Flowchart ...

Page 36: ...ts configure the I 2 S clock pin SCK as a clock output to allow the ISD3900 to provide an oscillator output to another device such as the host microcontroller Table 12 1 Clock Configuration Register Description CLK_CFG Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CLK_OUT 1 0 CLK_N_DIV 1 0 CLK_M_DIV 1 0 CLK_INP_SEL 1 0 00 11 01 00 Default 0x34 Internal clock with internal reference PLL active fo...

Page 37: ...of the status register refer to the following conditions PD If this bit is high then the device is powered down The DBUF_RDY bit will be low but all device output pins will be high impedance When PD is high only the READ_STATUS READ_INT and PWR_UP commands are accepted If any other command is sent it is ignored and no interrupt for an error is generated DBUF_RDY in PD this bit is low indicating th...

Page 38: ...llowing conditions INT an interrupt has been generated The interrupt is cleared by the READ_INT command PK_INT Indicates a peak detection interrupt has occurred Input peak detector can be configured to generate an interrupt when signal level exceeds a certain threshold MPT_ERR Indicates a memory protection error Digital access attempted for protected memory WR_FIN indicates a digital write command...

Page 39: ...t ADPCM Ratio to Fs 4 ISD provides a powerful software tool Voice Prompt Editor to help the user build their project and ease the configuration of the ISD3900 Configuration register CFG0 controls the sample rate and compression algorithm during message record operations It can also override sample rate setting for playback by setting bit 0 of CFG1 high SR 2 0 CFG0 7 5 controls the sample rate and ...

Page 40: ...iguration Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FIFO Over run FIFO Under run CFG0_READ LAT_ADC NRMP SRSIL SRCFG Default 0x00 Sample rate is set by the recorded audio header Whenever a change in sample rate is detected between two consecutive messages a period of silence is automatically inserted If an audio playback finishes at a non zero level the input to the signal path will ...

Page 41: ...e used during a SPI_DAC operation to check whether data sent to ISD3900 was corrupted This signal is latched and is reset by writing a 1 followed by a 0 to CFG1 7 the FIFO Over run bit FIFO Over run When read a high indicates that the audio FIFO has over run that is audio data from the signal path could not be processed fast enough to keep audio integrity and data was lost This is a normal conditi...

Page 42: ...Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 VOLC 7 0 Default 0x00 0 dB attenuation to the output signal volume Configuration register CFG3 sets the output signal volume Setting 0 has 0dB attenuation Each subsequent step provides 0 25dB of attenuation Table 12 14 CFG4 Register CFG4 Configuration Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 OFF_COMP AGC_EN ADC_IN Default 0x00 Disable the ADC input to ...

Page 43: ... input summation amplifier SUM1 PU_OP_SUM Powers up the output summation amplifier SUM2 PU_ADC Powers up the analog to digital converter ADC PU_DAC Powers up the digital to analog converter DAC Table 12 16 AUXIN Gain Configuration AUXIN_GAIN AUXIN_GAIN 1 0 Gain dB 00 0 01 3 10 6 11 9 Table 12 17 CFG6 Register CFG6 Configuration Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 AUX_SEL 1 0 A...

Page 44: ... CFG7 Configuration Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MIC_EN AUD_IOUT_RMPDN AUD_IOUT_RMPUP OUT_SUM 1 0 ADC_SEL 1 0 Default 0x00 Input source to the analog to digital converter ADC ANAIN Input source to the SUM2 mixer ANAIN Disable the ramp up down function on the current driver ANAIN and ANAOUT are used as single ended MIC inputs instead of differential MIC inputs Configurat...

Page 45: ...of pins ANAIN and ANAOUT as differential MIC inputs In this mode the ANAIN and ANAOUT pins become MIC and MIC and allow a differential input to be applied to the ADC The maximum level for this input is 1Vpp measured differentially This configuration is designed to be used in conjunction with the AGC to amplify microphone signals while achieving good common mode rejection of supply noise No mixing ...

Page 46: ... WS 0 channel to the signal path I 2 S_R_IN Enables I 2 S input from the right WS 1 channel to the signal path I 2 S_L_OUT Enables signal path output to the left WS 0 I 2 S channel I 2 S_R_OUT Enables signal path output to the right WS 1 I 2 S channel In addition to this basic functionality these bits are decoded to determine the whether mixing or feed through occurs in the I 2 S path See I 2 S se...

Page 47: ...lume releases volume decreases AGC_ATK 2 0 Determines the attack rate of the gain of the AGC This is the rate at which gain is reduced when the AGC output is larger than the target range Attack time is the time it takes for the AGC gain to ramp down AGC_REL 2 0 Determines the release rate of the gain of the AGC This is the rate at which gain is increased when the AGC output is below target range R...

Page 48: ... target signal range Hold time is the time delay before the AGC gain beginning to ramp up AGC_NG 2 0 Determines the level of the noise gate for AGC gain control When the peak detector level falls below the noise gate no gain changes are applied Level is referred to a full scale digital input which is 1Vpp at 0dB analog gain AGC_PKREL 1 0 Sets the release time of the input peak detector Table 12 30...

Page 49: ...e AGC_IG_EN 1 and AGC_EN 0 AGC_IG_EN Enables the AGC initial gain setting feature If AGC_IG_EN 0 then initial gain of the AGC is 0dB If AGC is activated AGC_EN 1 then gain will adjust according to the AGC algorithm Note When AGC is disabled AGC_EN 0 the last gain will continue to be applied to the ADC input To reset the ADC gain back to 0dB user must write AGC_IG 8 AGC_IE_EN 1 Table 12 33 AGC Init...

Page 50: ...errupt Configuration register CFGF controls the functionality of the peak detection interrupt PK_DET_LEV 6 0 Threshold level for the peak detection interrupt When peak detector exceeds this limit an interrupt is generated PK_DET_IE Enables the peak detection interrupt Table 12 36 Peak Detector Interrupt Level Peak Detector Interrupt Level PK_DET_LEV 6 0 Level dBFS Level mVp 0 54 3 1 1 48 2 1 9 8 3...

Page 51: ...Register CFG13 Configuration Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ADC_VAL 15 8 Configuration register CFG12 and CFG13 are a read only registers to query current output of the ADC converter ADC_VAL 15 0 Current value of the ADC converter For reliable read back the ADC_LAT bit should first be set high to latch this value Table 12 41 CFG14 Register CFG14 Configuration Register Bit...

Page 52: ... hold is active FAST_DEC High if peak signal level is 90 causing a fast decrement of gain DEC High if peak signal level is 81 25 FS causing a decrement of gain INC High if peak signal level is less than 80 FS causing gain to increment unless HOLD or NOISE is active AGC_GAIN 1 3 Additional bits of resolution of AGC_GAIN setting of CFGE Table 12 44 CFG17 Register CFG17 Configuration Register Bit 7 B...

Page 53: ... that when conducting DIG_WRITE SPI_PCM_WRITE and SPI_SND_DEC commands that the RDY bit of the status register is latched on SPI byte boundaries for correct read back PLL_LOCK Indicates that the PLL is locked If this bit is zero it indicates the PLL is attempting to lock on the input clock Read Only Table 12 45 CFG18 Register CFG18 Configuration Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 B...

Page 54: ...n the digital mode PWM When operating in the digital mode all remaining bits in CFG18 are don t care and have no effect upon the operation In the digital mode of operation speaker driver is controlled by PWM_OUT CFG2 2 The figure below shows an example of BTL setting from the AUX_MUX AUDOUT DAC AUXOUT PWM Control AUDOUT AUXOUT SPK SPK SUM2 SUM2_MUX AUD_MUX AUX_MUX SPK _MUX SPK _MUX From Digital Pa...

Page 55: ...gested initial configuration value 0x00 set to input output disabled 3 This register sets Output Enable to GPIO 1 output enabled 0 output disabled Table 12 48 CFG1B Register CFG1B Configuration Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 GPIO7 PE GPIO6 PE GPIO5 PE GPIO4 PE GPIO3 PE GPIO2 PE GPIO1 PE GPIO0 PE Default N A Suggested initial configuration value 0xFF pull up down enabled 3...

Page 56: ...PS GPIO3 PS GPIO2 PS GPIO1 PS GPIO0 PS Default N A Suggested initial configuration value 0xFF set to pull up 3 This register selects Pull up or pull down when PE is 1 1 pull up 0 pull down Table 12 51 CFG1F Register CFG1F Configuration Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 GPIO7 SDI AF GPIO6 SCK AF GPIO5 WS AF GPIO4 SDO AF Default N A Suggested initial configuration value 0x00 3...

Page 57: ...VP Rn Table 12 55 CFG23 Register CFG23 Configuration Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R1 15 8 for PlayVP Rn Table 12 56 CFG24 Register CFG24 Configuration Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R2 7 0 for PlayVP Rn Table 12 57 CFG25 Register CFG25 Configuration Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R2 15 8 for PlayVP Rn Table 12 58 CFG26...

Page 58: ...VP Rn Table 12 61 CFG29 Register CFG29 Configuration Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R4 15 8 for PlayVP Rn Table 12 62 CFG2A Register CFG2A Configuration Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R5 7 0 for PlayVP Rn Table 12 63 CFG2B Register CFG2B Configuration Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R5 15 8 for PlayVP Rn Table 12 64 CFG2C...

Page 59: ...t 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R7 15 8 for PlayVP Rn 12 4 DEVICE IDENTIFICATION REGISTERS By sending the command READ_ID the device responds with a four byte identification The first byte reports the 3900 family version The following three bytes are a JEDEC compliant code indicating the memory type The first byte is the manufacturer code which is 0xEF for Winbond The following byte is for...

Page 60: ... A offset by OFF sectors PLAY_SIL 0xA8 LEN 7 0 Play silence for LEN 32ms STOP 0x2A STOP current playback or record operation ERASE_MSG 0x3E A 23 16 A 15 8 A 7 0 Erase message starting at address A SPI_PCM_WRITE 0xAA D0 7 0 D0 15 8 D1 7 0 D1 15 8 Dn 7 0 Dn 15 8 Send 16 bit PCM audio data low byte high byte to I3900 via SPI interface SPI_PCM_READ 0xAC D0 7 0 D0 15 8 D1 7 0 D1 15 8 Dn 7 0 Dn 15 8 Rec...

Page 61: ...4 CFG_CLK 7 0 Set clock configuration register RD_CLK_CFG 0xB6 XX Read clock configuration register WR_CFG_REG 0xB8 REG 7 0 D0 7 0 Dn 7 0 Write data D0 Dn to configuration register s starting at configuration register REG RD_CFG_REG 0xBA REG 7 0 XX XX Read configuration register s starting at configuration register REG Each command will be accepted if certain conditions are met as in the following...

Page 62: ...S 0x40 x x x x x x x READ_INT 0x46 x x x x x x x RD_MSG_ADD 0x42 0 1 x x x x x RD_MSG_LEN 0x44 0 1 x x x x x READ_ID 0x48 0 1 x x x x x DIG_READ 0xA2 0 1 x x x x x DIG_WRITE 0xA0 0 1 x x x x x ERASE_MEM 0x24 0 1 x x 0 0 0 CHIP_ERASE 0x26 0 1 x x 0 0 0 PWR_UP 0x10 1 0 x x x x x PWR_DN 0x12 0 1 x x x x x SET_CLK_CFG 0xB4 0 1 x x 0 0 0 RD_CLK_CFG 0xB6 0 1 x x x x x WR_CFG_REG 0xB8 0 1 x x x x x RD_CF...

Page 63: ...t will be generated and the command ignored If command is terminated after the command byte is sent no interrupt will be generated Once playback is finished a CMD_FIN interrupt will be generated 13 1 2 Play Voice Prompt Rn n 0 7 PLAY_VP Rn Byte Sequence Host controller 0xAE n 0 7 ISD3900 Status Byte Status Byte Description Play Voice Prompt Index Rn Interrupt Generation CMD_ERR if not accepted CMD...

Page 64: ...vice fills available memory This command initiates a record operation Before execution of command a valid signal path must be set up and the device must have space in the audio command buffer If device is or becomes full an interrupt is generated and the FULL_ERR bit of the interrupt status register is set Recording is terminated by issuing a STOP command After the operation is complete the begin ...

Page 65: ...ss is complete 13 1 6 Play Message at Address PLAY_MSG Byte Sequence Host controller 0x3C A 23 16 A 15 8 A 7 0 OFF 15 8 OFF 7 0 ISD3900 Status Byte Status Byte Status Byte Status Byte Status Byte Status Byte Description Initiate a managed record starting at sector address A 4096 OFF Interrupt Generation CMD_ERR if not accepted CMD_FIN when playback complete ADDR_ERR if invalid address sent This co...

Page 66: ...CMD_ERR interrupt will be generated and the command ignored If command is terminated after the command byte is sent no interrupt will be generated Once silence play is finished a CMD_FIN interrupt will be generated 13 1 8 Stop Command STOP Byte Sequence Host controller 0x2A ISD3900 Status Byte Description Stop current audio command and flush command buffer Interrupt Generation Command itself does ...

Page 67: ...the erase is finished If a DIG_RD or DIG_WR command is sent to the device RDY BSYB pin will hold off any data transfer until the ERASE_MSG has completed 13 1 10 SPI Write PCM Data SPI_PCM_WRITE Byte Sequence Host controller 0Xaa D0 7 0 D0 15 8 Dn 7 0 Dn 15 8 ISD3900 Status Byte Description Write audio data via SPI interface Interrupt Generation OVF_ERR if RDY BSY violated This command allows the u...

Page 68: ...espond with a CMD_FIN interrupt RDY BSYB pin will handshake dataflow to the sample rate set by the audio configuration register If host cannot keep up with data rate audio will be corrupt Once audio data is sent raise SSB high and device will continue to play zero samples out the signal path until reconfigured or more data is sent FIFO SPI OUT SPI IN UP SAMPLE FILTER DOWN SAMPLE FILTER DECOMPRESSO...

Page 69: ...erated and zero will be sent as data If the valid play command in step 2 is ExeVM then a CMD_FIN interrupt will be generated at the end of voice macro FIFO SPI OUT SPI IN UP SAMPLE FILTER DOWN SAMPLE FILTER DECOMPRESSOR COMPRESSOR MEMORY CONTROL Figure 13 3 SPI Playback If reading audio data from the analog inputs feed through SPI then 1 the path must be set up for SPI output from the signal path ...

Page 70: ...0 ISD3900 Status Byte Description Write compressed audio data via SPI interface Interrupt Generation OVF_ERR if RDY BSYB violated This command allows the user to send compressed audio data in a byte formatted bit stream down the SPI interface to the de compressor and signal path Before execution of command 1 a valid signal path must be set up Valid paths are similar to a standard playback 2 Multip...

Page 71: ...gital memory operations between SPI_SND_DEC operations however care must be taken to maintain the required data rate to avoid audio corruption 13 1 13 SPI Receive Encoded Data SPI_RCV_ENC Byte Sequence Host controller 0xC2 ISD3900 Status Byte D0 7 0 D1 7 0 Dn 7 0 Description Read compressed audio data via SPI interface Interrupt Generation OVF_ERR if RDY BSYB violated This command allows the user ...

Page 72: ...ored then an OVF_ERR interrupt is generated The SPI_RCV_ENC command is accepted if no current play or record operation is active If command is not accepted a CMD_ERR interrupt will be generated It is possible to perform digital memory operations between SPI_RCV_ENC operations however care must be taken to maintain the required data rate to avoid audio corruption 13 2 DEVICE STATUS COMMANDS This se...

Page 73: ...active The INT bit of the status register along with any status error bits will return inactive This command is accepted whenever device is powered up 13 2 3 Read Recorded Message Address Details RD_MSG_ADD Byte Sequence Host controller 0x42 X X X X X ISD3900 STATUS0 A 23 16 A 15 8 A 7 0 LEN 15 8 LEN 7 0 Description Reports the start sector address A 4096 of current message and length LEN in 4kByt...

Page 74: ...uld return LEN 3 A subsequent PLAY_MSG SA 2 command would restart the playback from the beginning of the sector where playback was stopped that is send PLAY_MSG SA LEN 1 Now if a STOP was issued after an additional three sectors of playback message is now playing the sixth sector RD_MSG_LEN would return LEN 6 13 2 5 Read I3900 ID READ_ID Byte Sequence Host controller 0x48 0xXX 0xXX 0xXX 0xXX ISD39...

Page 75: ...igh The user should check RDY BSYB pin before every byte is sent read including the command and address bytes As many bytes of data as required can be read command is terminated by raising SSB high finishing the SPI transaction If an attempt is made to read past the end of memory status byte will be read back The command will always be accepted and RDY BSYB pin will go low until any active digital...

Page 76: ...tive Please note that for ISD3900 Digital Write operation can only support up to 64M bits User should avoid trying to write memory beyond 64Mbit boundary 13 3 3 Erase Memory ERASE_MEM Byte Sequence Host controller 0x24 SA 23 16 SA 15 8 SA 7 0 EA 23 16 EA 15 8 EA 7 0 ISD3900 Status Status Status Status Status Status Status Description Erases memory from sector containing SA to sector containing EA ...

Page 77: ... If a DIG_RD or DIG_WR command is sent to the device RDY BSYB pin will hold off any data transfer until the CHIP_ERASE has completed When CHIP_ERASE is in progress the Status bit 0 CMD_BSY goes high Users could poll the status to see if the erasing is done 13 4 DEVICE CONFIGURATION COMMANDS This section describes 6 commands used to configure the ISD3900 These commands are used to Set up the clocki...

Page 78: ...ve commands finish This command powers down the device If the device is currently executing a command the device will powers down when the command finishes If sent while recording without a STOP command sent first then device will record until full then power down If playing or executing a voice macro device will power down after playback is finished The PWR_DN command will not generate an interru...

Page 79: ...ers are loaded See Section 12 3 for details on configuration registers There are forty eight configuration registers in the ISD3900 REG0 REG2F 13 4 6 RD_CFG_REG Read Configuration Register RD_CFG_REG Byte Sequence Host controller 0xBA REG 7 0 X X ISD3900 STATUS0 D0 Dn Description Reads configuration register CFG REG and outputs to SPI as D0 Data bytes 1 n can be read sequentially from CFG REG 1 to...

Page 80: ...peration is not implied at these conditions 14 2 OPERATING CONDITIONS OPERATING CONDITIONS INDUSTRIAL PACKAGED PARTS CONDITIONS VALUES Operating temperature range Case temperature 40 C to 85 C Supply voltage VDD 1 2 7V to 3 6V Ground voltage VSS 2 0V Input voltage VDD 1 0V to 3 6V Voltage applied to any pins VSS 0 3V to VDD 0 3V NOTES 1 VDD VCCA VCCD VCCPWM 2 VSS VSSA VSSD VSSPWM 14 3 DC PARAMETER...

Page 81: ...ISD3900 Publication Release Date Dec 10 2013 81 Revision 1 5 Standby Current ISB 1 10 µA VDD 3 6V Input Leakage Current IIL 1 µA Force VDD Notes 1 Conditions VDD 3V TA 25 C unless otherwise stated ...

Page 82: ...14 4 2 Inputs ANAIN MICIN PARAMETER SYMBOL MIN TYP 1 MAX UNITS CONDITIONS ANAIN Input Voltage VANAIN 10 1000 mV Peak to Peak 2 ANAIN Feed Back Resistance RANA FB 40 100 KΩ MICIN Input Voltage VMICIN 5 500 mV Peak to Peak 2 Notes 1 Conditions VDD 3V TAB 25 C unless otherwise stated 2 Depends on Gain Setting AUXIN PARAMETER SYMBOL MIN TYP 1 MAX UNITS CONDITIONS AUXIN Input Voltage VAUXIN 1000 mV Pea...

Page 83: ...ssage weighted 4 Measured with 1KHz 100 mVpp sine wave applied to VCCA pins AUDOUT PARAMETER SYMBOL MIN TYP 1 MAX UNITS CONDITIONS SINAD AUXIN to AUDOUT 5 SINADAUXIN_AUDOUT 80 dB Load 5K 2 3 SINAD ANAIN to AUDOUT 5 SINADANAIN_AUDOUT 80 dB Load 5K 2 3 PSRR 5 PSRRAUDOUT 40 dB 4 DC Bias 5 VBIAS_AUDOUT 1 2 V Minimum Load Impedance 5 RL AUDOUT 5 KΩ Maximum Load Capacitance 5 CL AUDOUT 0 1 nF Output Cur...

Page 84: ... 0 360 mW Load 8Ω 2 62 5 mW Load 8Ω 4 5 THD AUXIN to SPK SPK THD 1 Load 8Ω 2 Minimum Load Impedance RL SPK 4 8 Ω Notes 1 Conditions Vcc 3V TA 25 C unless otherwise stated 2 1 Vpp 1KHz signal applied at AUXIN ANAIN with 0dB gain setting to PWM output 3 All measurements are C message weighted 4 Full scale 1K sine wave as input playback from memory with 0dB gain setting to BTL output 5 2 Vpp 1KHz sig...

Page 85: ...cord path for analog or digital audio inputs The data presented is for a master sample rate Fs 32kHz For other values of Fs Fsub scales accordingly There is a built in high pass filter with cutoff 200Hz following the ADC filter The graphs below show a combined effect Record Frequency Response Fs 32kHz Fsub 4kHz Record Frequency Response Fs 32kHz Fsub 5 33kHz ...

Page 86: ...ISD3900 Publication Release Date Dec 10 2013 86 Revision 1 5 Record Frequency Response Fs 32kHz Fsub 6 4kHz Record Frequency Response Fs 32kHz Fsub 8kHz Record Frequency Response Fs 32kHz Fsub 12 8kHz ...

Page 87: ...ISD3900 Publication Release Date Dec 10 2013 87 Revision 1 5 Record Frequency Response Fs 32kHz Fsub 16kHz Record Frequency Response Fs 32kHz Fsub 32kHz Playback Frequency Response Fs 32kHz Fsub 4kHz ...

Page 88: ...D3900 Publication Release Date Dec 10 2013 88 Revision 1 5 Playback Frequency Response Fs 32kHz Fsub 5 33kHz Playback Frequency Response Fs 32kHz Fsub 6 4kHz Playback Frequency Response Fs 32kHz Fsub 8kHz ...

Page 89: ...D3900 Publication Release Date Dec 10 2013 89 Revision 1 5 Playback Frequency Response Fs 32kHz Fsub 12 8kHz Playback Frequency Response Fs 32kHz Fsub 16kHz Playback Frequency Response Fs 32kHz Fsub 32kHz ...

Page 90: ...SCKL SCLK Low Pulse Width 25 ns TRISE Rise Time for All Digital Signals 10 ns TFALL Fall Time for All Digital Signals 10 ns TSSBS SSB Falling Edge to 1 st SCLK Falling Edge Setup Time 30 ns TSSBH Last SCLK Rising Edge to SSB Rising Edge Hold Time 30ns 50us TSSBHI SSB High Time between SSB Lows 20 ns TMOS MOSI to SCLK Rising Edge Setup Time 15 ns TMOH SCLK Rising Edge to MOSI Hold Time 15 ns TZMID ...

Page 91: ...2 ns TRBCD Delay Time from RDY BSYB Rising Edge to SCLK Falling Edge 0 ns 14 4 6 I 2 S Timing TWSH TWSS MSB TSDIS TSDOD TSCKH TSCKL TWSH TWSS MSB MSB MSB LSB LSB TSDIH TSCK TRISE TFALL IS_SCK IS_WS IS_SDI IS_SDO Figure 0 2 I 2 S Timing SYMBOL DESCRIPTION MIN TYP MAX UNIT TSCK IS_SCK Cycle Time 60 ns TSCKH IS_SCK High Pulse Width 25 ns TSCKL IS_SCK Low Pulse Width 25 ns TRISE Rise Time for All Digi...

Page 92: ...ALL Fall Time for All Digital Signals 10 ns TWSS WS to IS_SCK Rising Edge Setup Time 20 ns TWSH IS_SCK Rising Edge to IS_WS Hold Time 20 ns TSDIS IS_SDI to IS_SCK Rising Edge Setup Time 15 ns TSDIH IS_SCK Rising Edge to IS_SDI Hold Time 15 ns TSDOD Delay Time from IS_SCLK Falling Edge to IS_SDO 12 ns ...

Page 93: ...PIO1 GPIO0 4 5 6 7 30 31 32 38 MISO SCLK SSB MOSI INTB RDY BSYB RESET 13 14 15 16 25 26 27 MIC MIC AUXIN VSSD VCCD VCCD 0 1 uF 47 uF VCCD 17 21 19 VSSD_PWM VCCD_PWM VCCD_PWM high pulse of 50ms VREG 12 46 45 Digital ground Analog ground 0 1 uF 47 VCCD 10K VCCA 220uF 1 5 K 0 1uF 1 5 K 0 1uF 1 5 K MIC data flow control SPI Type III SPK SPK 18 20 100 4 7K 0 1uF 200 pF AUXOUT 42 AUDOUT 41 430 0 1uF VCC...

Page 94: ...ISD3900 Publication Release Date Dec 10 2013 94 Revision 1 5 16 PACKAGE SPECIFICATION 16 1 48 LEAD LQFP 7X7X1 4MM FOOTPRINT 2 0MM ...

Page 95: ...ISD3900 Publication Release Date Dec 10 2013 95 Revision 1 5 17 ORDERING INFORMATION I3900 FYI Lead Free Package Type F 48L LQFP Y Green RoHS Compliant I Industrial 40 C to 85 C ...

Page 96: ...SPI timing TSSBH maximum 50us MICIN input signal 500mV Revise Block Diagram add BTL block Revise Application Diagram 0 80 Feb 10 2009 Update Remove the Preliminary watermark Output low high voltage 0 82 Nov 20 2009 Update Block Diagram 1 0 July 1 2010 Update crystal configuration 1 1 Dec 13 2010 Fix the typo of internal memory to external memory 1 3 May 6 2011 Add Absolute Maximum Ratings 1 4 Aug ...

Page 97: ... or inability to use the contents of this documents even if Nuvoton has been advised of the possibility of such damages Application examples and alternative uses of any integrated circuit contained in this publication are for illustration only and Nuvoton makes no representation or warranty that such applications shall be suitable for the use specified The 100 year retention and 100K record cycle ...

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