ISD3900
Publication Release Date: Dec 10, 2013
- 30 -
Revision 1.5
10
CLOCK GENERATION
The ISD3900 can derive its master clock from five sources:
1. An external crystal (or resonator) oscillator interface.
2. An external clock input (applied to pin XTALIN and left the XTALOUT unconnected)
3. An internal oscillator controlled by an external resistor (attached to pin XTALIN and GND).
4. An internal oscillator with internal reference.
5. The SCK clock of the I
2
S interface.
Regardless of source, the selected clock is fed to a phase-locked loop (PLL) to generate the internal
master clock (MCLK) of the ISD3900.
IIS_SCK
XTAL_CLK
M
U
X
SEL_CLK_INP<1:0>
MCLK
PLL_REF_CLK
PLL_OUT_CLK
OSC_CLK
M
N
PFD
CHARGE
PUMP
LOOP
FILTER
VCO
2
F
OSC
Figure 10-1 PLL Clock Generation on ISD3900
The goal of clock generation is to generate a master clock rate (MCLK) at 512x the master sample
rate (Fs). A table of supported master clock and sample rates is shown below. The master sample
frequency can be expressed by the formula:
M
N
F
F
OSC
MCLK
2
where
}
3
,
2
,
1
{
M
and
}
32
,
16
,
8
{
N
512
1
MCLK
s
F
F
Table 10-1 Master Clock and Sample Rates
MCLK (MHz)
Fs (kHz)
16.384
32
24.576
48
22.5792
44.1
For the above master sample rates, Fs, record and playback is available at fixed ratios of the master
sample rate.
