Nintendo 1504166 - Game Boy Advance SP Edition Console Programming Manual Download Page 64

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AGB Programming Manual

Rendering Functions

D.C.N. AGB-06-0001-002B4

[d11-10] OBJ Mode

Specifies whether an OBJ is a normal OBJ or a semitransparent OBJ.

A normal OBJ is specified by 00, a semi-transparent OBJ by 01, and an
OBJ window by 10.

A value of 11 is a prohibited code, so care should be taken to prevent this
setting.

When a semi-transparent OBJ is specified, color special effects
processing can be performed. For information on color special effects,
see “9 Color Special Effects”.

OBJs for which an OBJ window specification is used are not displayed as
normal OBJs; dots with non-zero character data are used as the OBJ
window.

[d09] Rotation/Scaling Double-Size Flag

OBJs are limited in size by the OBJ field (8x8 - 64x64 dots), and the
character data may surpass the boundaries of this field when rotated.

This problem can be avoided by implementing a pseudo double-size for
the OBJ field, by setting the double-size flag to 1.

With this setting, the OBJ does not surpass the boundaries of the OBJ
field even if the OBJ display is magnified by up to two-fold.

Summary of Contents for 1504166 - Game Boy Advance SP Edition Console

Page 1: ...April 2 2001 AGB Programming Manual Version 1 1 1999 2001 Nintendo of America Inc ...

Page 2: ...s also protected under the copyright laws of the United States and other countries No part of this document may be released distributed transmitted or reproduced in any form or by any electronic or mechanical means including information storage and retrieval systems without permission in writing from Nintendo 1999 2001 Nintendo of America Inc TM and are trademarks of Nintendo ...

Page 3: ...eously by overlapping them using the CPU L and R buttons have been added to the Controller The broader range of control provided also expands the breadth of game designs possible Although AGB uses a 32 bit RISC CPU whose computing performance and data processing capabilities far surpass those of Game Boy Color it consumes little power allowing approximately 15 hours of continuous play This is made...

Page 4: ...ing RAM Changed the bit structures of DMA control registers Deleted Infrared Communication functions Created the interrupt IME register and changed the bit structures of IE and IF registers Changed the number of colors that can be displayed to 32 768 Changed the specifications of Normal Serial Communication Bit width communication speed Changed the specifications of Multi SIO Communication UART sy...

Page 5: ...ttributes of timer setting values register from W to R W Added one sentence to 1 of 15 2 1 Normal Interrupt and 15 2 2 Multiple Interrupts respectively Emphasized the prohibition of use of cable for normal SIO communication 0 4 1 6 06 26 2000 Modified the connection diagram of the multi play cable Added the transition diagram of the multi play communication data Modified the description of 16 Bit ...

Page 6: ...pecific expression Cautions for Added a description of X coordinate and Y coordinate for OAM Added the diagram to Y coordinate Revised the description of the pre fetch buffer flag in the Game Pak memory wait control register Added cautions to the description of the input output select flag in the R register of general communication 1 01 2 01 2001 Modified the description of pin 31 in the Game Pak ...

Page 7: ...e Revised the caution for normal serial communication Revised the caution for communication function Revised the summary of normal serial communication in the communication function chapter and added additional description Added additional description in the caution for the selection of communication function in the communication function chapter Emphasized that unless general purpose communicatio...

Page 8: ...h DM 0 3 CNT_L à à DMA 0 3 CNT_L 0Bah DM 0 3 CNT_H à à DMA 0 3 CNT_H Timer Related 100h TM 0 3 D à à TM 0 3 CNT_L 102h TM 0 3 CNT à à TM 0 3 CNT_H Communication Related 134h R à à RCNT 128h SCCNT_L à à SIOCNT 12Ah SCCNT_H à à SIODATA8 Normal serial UART communication SIOMLT_SEND Multi play communication 120h SCD0 à à SIODATA32_L Normal serial communication SIOMULTI0 Multi play communication 122h S...

Page 9: ... 19 3 2 2 Game Pak Memory 20 3 3 GAME PAK MEMORY WAIT CONTROL 21 3 3 1 Access Timing 23 3 3 2 Game Pak Bus 24 4 LCD 25 4 1 LCD STATUS 26 4 1 1 V Counter 26 4 1 2 General LCD Status 27 5 IMAGE SYSTEM 29 5 1 BG MODES 31 5 1 1 Details of BG Modes 31 5 1 2 VRAM Memory Map 32 6 RENDERING FUNCTIONS 33 6 1 CHARACTER MODE BG BG MODES 0 2 33 6 1 1 BG Control 33 6 1 2 Mosaic Size 39 6 1 3 VRAM Address Mappi...

Page 10: ...2 6 3 4 OBJ Rotation Scaling Feature 70 6 4 DISPLAY PRIORITY OF OBJ AND BG 72 7 COLOR PALETTES 73 7 1 COLOR PALETTE OVERVIEW 73 7 2 COLOR PALETTE RAM 74 7 3 COLOR DATA FORMAT 76 8 WINDOW FEATURE 77 8 1 WINDOW POSITION SETTING 77 8 2 WINDOW CONTROL 78 9 COLOR SPECIAL EFFECTS 80 9 1 SELECTION OF COLOR SPECIAL EFFECTS 80 9 2 COLOR SPECIAL EFFECTS PROCESSING 82 10 SOUND 84 10 1 SOUND BLOCK DIAGRAM 84 ...

Page 11: ...GENERAL PURPOSE COMMUNICATION 148 13 5 JOY BUS COMMUNICATION 150 13 6 AGB GAME LINK CABLE 154 14 KEY INPUT 155 14 1 KEY STATUS 155 14 2 KEY INTERRUPT CONTROL 155 14 2 1 Interrupt Conditions 156 15 INTERRUPT CONTROL 157 15 1 SYSTEM ALLOCATED AREA IN WORK RAM 159 15 2 INTERRUPT OPERATION 160 15 2 1 Normal Interrupt 160 15 2 2 Multiple Interrupts 161 16 POWER DOWN FUNCTIONS 163 16 1 STOP FUNCTION 163...

Page 12: ...erm Used 8 bits byte 16 bits half word 32 bits word 2 Symbols The attributes of bits used in bit operations are represented as follows 3 Abbreviations Nintendo s game hardware is abbreviated as follows Ø DMG Game Boy Ø CGB Game Boy Color Ø AGB Game Boy Advance Ø DOL Nintendo GameCube Read write bit A readable and writable bit Read only bit A bit that is readable but not writable Write only bit A b...

Page 13: ...r it cannot operate at the same time as the AGB CPU Memory System ROM 16 Kbytes and 2 Kbytes for CGB System ROM Working RAM 32 Kbytes CPU External 256 Kbytes 2 wait VRAM 96 Kbytes OAM 64 bits x 128 Palette RAM 16 bits x 512 256 colors for OBJ 256 colors for BG Game Pak memory Up to 32 MB mask ROM or flash memory EEPROM Up to 512 Kbits SRAM or flash memory Display 240 x 160 x RGB dots 32 768 colors...

Page 14: ...d with a 32 pin connector for Game Pak connection When a Game Pak is inserted AGB automatically detects its type and switches to either CGB or AGB mode The following Game Paks operate on the AGB system 1 DMG Game Paks DMG CGB dual mode Game Paks and CGB dedicated Game Paks 2 AGB dedicated Game Paks Game Paks that only function with AGB ...

Page 15: ...32 32 32 32 32 32 16 16 16 16 16 16 16 16 16 16 16 R 16 32 W 16 32 R 8 16 32 R 8 16 32 and W 8 16 32 mean that you can access an area of 8bits 16bits 32bits when reading and writing respectively ROM 16KByte Palette RAM 16bit x 512 Priority Evaluation Circuit OBJ Processing Circuit OAM 64bit x 128 BG Processing Circuit R 8 16 32 W 8 16 32 32 32 R 8 16 32 W 8 16 32 R 8 16 32 W 8 16 32 R 8 16 32 W 8 ...

Page 16: ...2bit SIO General Purpose Port Multi SIO UART JOY AGB Unit LCD Module 4 194MHz System 16 78MHz A B SELECT START R L 5V DMG CGB 3 3V AGB Switch Between AD Bus General Purpose Bus Game Pak Power 3 3V AGB 5V DMG CGB Gane Pak External Unit 3 3V 5V Voltage Detection Circuit AA Alkaline Battery AA Alkaline Battery Power Switch DC DC Converter and Regulator 13 6V 5V 3 3V 2 5V 15V VRAM 98KByte 16bit Bus CP...

Page 17: ... 8 16 32 Internal registers 32 16 32 16 32 8 16 32 8 16 32 Game Pak ROM Mask ROM Flash Memory 16 16 32 16 32 8 16 32 16 32 Game Pak RAM SRAM Flash Memory 8 8 8 Good execution efficiency is obtained when programs that operate from the Game Pak use 16 bit instructions 16 bit compiler and those that operate from CPU Internal Working RAM use 32 bit instructions 32 bit compiler 2 4 Little Endian In the...

Page 18: ...tate 2 32 MB Game Pak ROM Wait State 1 32 MB Game Pak ROM Wait State 0 32 MB Game Pak Memory AGB Internal Memory Images 0E000000h 0C000000h 0A000000h 08000000h 07000000h 06000000h 05000000h 04000000h 02000000h 00000000h Flash Memory 1 Mbit Mask ROM 255 Mbits Flash Memory 1 Mbit Mask ROM 255 Mbits Flash Memory 1 Mbit Mask ROM 255 Mbits 00003FFFh 0203FFFFh 050003FFh 06017FFFh 070003FFh 0FFFFFFFh 0E0...

Page 19: ...nal Working RAM The 256 Kbytes from 02000000h is CPU External Working RAM Its specifications are 2 Wait 16 bit Bus 3 CPU Internal Working RAM The 32 Kbytes from 03000000h is CPU Internal Working RAM It is used to store programs and data 4 I O and Registers This area is used for various registers 5 Palette RAM The 1 Kbyte from 05000000h is palette RAM It is used to assign palette colors 6 VRAM The ...

Page 20: ...ry of varying access speeds in Game Pak ROM to be accessed optimally The base addresses of the 3 spaces are 08000000h for Wait State 0 0A000000h for Wait State 1 and 0C000000h for Wait State 2 In addition the upper 1 Mbit of each space is allocated as flash memory This area is used primarily for saving data 2 Game Pak RAM The area beginning from 0E000000h is the Game Pak RAM area Up to 512 Kbits o...

Page 21: ...e 0 Wait Control Wait State 1 Wait Control Wait State 2 Wait Control PHI Terminal Output Control 00 No Output 01 4 19 MHz clock 10 8 38 MHz clock 11 16 76 MHZ clock Prefetch Buffer Flag 0 Disabled 1 Enabled Game Pak Type Flag WAITCNT d15 Game Pak Type Flag The System ROM uses this WAITCNT d14 Prefetch Buffer Flag When the Prefetch Buffer Flag is enabled and there is some free space the Prefetch Bu...

Page 22: ...ettings and wait cycles is as follows Use the appropriate settings for the device you are using Wait Cycles 2nd Access Wait Control Value 1st Access Wait State 0 Wait State 1 Wait State 2 000 4 2 4 8 001 3 2 4 8 010 2 2 4 8 011 8 2 4 8 100 4 1 1 1 101 3 1 1 1 110 2 1 1 1 111 8 1 1 1 After executing the System ROM when the User Program is started the Wait Control Value is 000 In the Game Pak Mask R...

Page 23: ...n the first access and 1 wait cycle on the second 1 Sequential Access 1st Access 3 wait cycles 2nd Access 1 wait cycle 3rd Access 1 wait cycle System Clock 16 78 MHz Wait Cycles AD Bus wait wait wait Address Data Data wait Data wait 2 Random Access 1st Access 3 wait cycles 1st Access 3 wait cycles System Clock 16 78 MHz Wait Cycles AD Bus wait wait wait Address Data wait Data wait wait Address ...

Page 24: ...rite Flag 4 RD Read Flag RD Read Flag 5 CS ROM Chip Selection CS 6 AD0 A0 7 AD1 A1 8 AD2 A2 9 AD3 A3 10 AD4 A4 11 AD5 A5 12 AD6 A6 13 AD7 A7 14 AD8 A8 15 AD9 A9 16 AD10 A10 17 AD11 A11 18 AD12 A12 19 AD13 A13 20 AD14 A14 21 AD15 Terminals used for both address lower and data A15 Address 22 A16 D0 23 A17 D1 24 A18 D2 25 A19 D3 26 A20 D4 27 A21 D5 28 A22 D6 29 A23 Address upper D7 Data 30 CS2 CS2 RA...

Page 25: ... dots 160 lines 228 lines 16 212µs 4 994ms Item Value Interval Display screen size Number of dots per horizontal line 240 dots 57 221 µs Number of horizontal lines 160 lines 11 749 ms Total number of dots Number of dots per horizontal line 308 dots 73 433 µs Number of horizontal lines 228 lines 16 743 ms Blanking Number of dots per horizontal blank 68 dots 16 212 µs Number of horizontal lines per ...

Page 26: ...ad which of the total of 228 LCD lines see previous figure is currently being rendered 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 VCOUNT 006h 0000h R Address Register Attributes Initial Value V counter value 0 227 A value of 0 227 is read A value of 0 159 indicates that rendering is in progress a value of 160 227 indicates a vertical blanking interval ...

Page 27: ...Blank Interrupt Request Enable Flag 0 Disable 1 Enable H Blank Interrupt Request Enable Flag 0 Disable 1 Enable V Counter Match Interrupt Request Enable Flag 0 Disable 1 Enable Attributes DISPSTAT d15 08 V Count Setting Can be used to set the value used for V counter evaluation and V counter match interrupts The range for this setting is 0 227 DISPSTAT d05 V Counter Match Interrupt Request Enable ...

Page 28: ...whether the V count setting and the V count register value match It is set while they match and automatically reset when they no longer match DISPSTAT d01 H Blank Status Can check whether a horizontal blanking interval is currently in effect DISPSTAT d00 V Blank Status Can check whether a vertical blanking interval is currently in effect ...

Page 29: ... 0 Enable OBJ Processing of all H Line Intervals 1 Disable OBJ Processing of H Line Display Intervals Only OBJ Character VRAM Mapping Format 0 2 dimensional 1 1 dimensional Forced Blank 0 Disable 1 Enable Individual Screens Display 0 OFF 1 ON H Blank Interval OBJ Processing Flag DISPCNT d15 OBJ Window Display Flag Master flag that controls whether the OBJ window is displayed For information on the...

Page 30: ...section 6 3 2 Character Data Mapping DISPCNT d05 H Blank Interval OBJ Processing Flag A setting of 0 executes OBJ Render Processing with all H Line intervals including H Blank intervals A setting of 1 executes OBJ Render Processing with the display intervals only and not for H Blank intervals Thus when the user accesses OAM or OBJ VRAM during an H Blank interval this bit needs to be set However al...

Page 31: ... to 1024 x 1024 256 256 1 O X O O O O 2 Yes 2 128 x 128 to 1024 x 1024 256 256 1 O X O O O O Bitmap Format BG Screen Features BG Mode Rotation Scaling No of Screens Size Frame Memory No of Colors 1 2 3 4 5 6 3 Yes 1 240 x 160 1 32 768 O X O O O O 4 Yes 1 240 x160 2 256 O X O O O O 5 Yes 1 160 x 128 2 32 768 O X O O O O Features 1 HV Scroll individual screens 4 Semitransparent 16 levels 2 HV Flip i...

Page 32: ...ter Data 16 Kbytes Frame Buffer 0 40 Kbytes BG Modes 0 1 and 2 BG Mode 3 BG Modes 4 and 5 06010000h 06014000h 0600A000h 06014000h 06000000h 06017FFFh BG0 BG3 Screen Data Maximum 32 Kbytes BG0 BG3 Shared Character Data Minimum 32 Kbytes and Users can map the screen and character data areas in the 64 Kbyte BG area in BG modes 0 1 and 2 For more information see section 6 1 3 VRAM Address Mapping of B...

Page 33: ...components of the BG screen are basic characters of 8 x 8 dots 6 1 1 BG Control There are 4 BG control registers corresponding to the maximum number of BG screens registers BG0CNT BG1CNT BG2CNT and BG3CNT Registers BG0CNT and BG1CNT are exclusively for text BG control while BG2CNT and BG3CNT also support BG rotation and scaling control The registers used by the BG modes are as follows BG Mode BG C...

Page 34: ... Control BG0 BG1 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 BG0CNT BG1CNT 008h 00Ah 0000h R W Address Register Attributes Initial Value Priority Specification 00 1st priority 01 2nd priority 10 3rd priority 11 4th priority Character Base Block 0 3 0 0 Screen Size Mosaic 0 Disable 1 Enable Color Mode 0 16 colors x 16 palettes 1 256 colors x 1 palette Screen Base Block 0 31 ...

Page 35: ...creen Size Mosaic 0 Disable 1 Enable Color Mode 0 16 colors x 16 palettes 1 256 colors x 1 palette Screen Base Block 0 31 Area Overflow Processing Flag 0 Transparent display 1 Wraparound display BG CNT d15 14 Screen Size Allows the screen size for the BG as a whole to be specified When a value other than the maximum is specified the remaining VRAM area can be used as a character data area Refer to...

Page 36: ...5 d14 0 1 Virtual Screen size 512 x 256 Display Screen 240 x 160 SC0 256 x 256 SC0 SC1 SC1 256 x 256 Display Screen 240 x 160 SC0 256 x 256 SC1 256 x 256 SC2 256 x 256 SC3 256 x 256 SC0 SC2 SC0 SC1 SC0 d15 d14 1 0 Virtual screen size 256 x 512 d15 d14 1 1 Virtual screen size 512 x 512 SC0 256 x 256 SC0 SC0 SC0 Display Screen 240 x 160 SC0 256 x 256 SC0 SC1 SC1 256 x 256 Display Screen 240 x 160 ...

Page 37: ...256 x 256 d15 d14 1 0 Virtual screen size 512 x 512 SC0 256 x 256 d15 d14 1 1 Virtual screen size 1024 x1024 Display Screen 240 x 160 SC0 1024 x 1024 SC0 or Transparent SC0 or Transparent SC0 or Transparent SC0 or Transparent Display Screen 240 x 160 SC0 512 x 512 SC0 or Transparent SC0 or Transparent SC0 or Transparent SC0 or Transparent SC0 or Transparent SC0 128 x 128 Display Screen 240 x 160 S...

Page 38: ...See section 6 1 3 VRAM Address Mapping of BG Data BG CNT d07 Color Mode Specifies whether to reference BG character data in 16 color x 16 palette format or 256 color x 1 palette format BG CNT d06 Mosaic Turns mosaic processing for BG on and off BG CNT d03 02 Character Base Block Specification Specifies the starting block in VRAM where the character data to be displayed in the BG is stored 4 steps ...

Page 39: ...ach large dot displayed Counting from the upper left most dot on the screen the number of dots equal to the mosaic size are used in the mosaic display The other dots are overwritten by the mosaic Please refer to the figure below If the mosaic size value is 0 a normal display is seen even if mosaic is turned on Mosaic Schematic 01 02 03 04 05 06 07 08 09 11 12 21 13 22 30 14 23 31 40 15 16 24 25 19...

Page 40: ...ing the character base block specification of the BG control register The amount of data depends on the number of character data items stored and the data format color formats 256 colors x 1 palette or 16 colors x 16 palettes 2 BG Screening Data The starting address for referencing BG screen data can be set using the screen base block specification of the BG control register The amount of data dep...

Page 41: ...se Block 31 Base Block 30 Base Block 29 Base Block 28 Base Block 27 Base Block 26 Base Block 25 Base Block 24 Base Block 2 8000h Base Block 23 Base Block 22 Base Block 21 Base Block 20 Base Block 19 Base Block 18 Base Block 17 Base Block 16 Base Block 1 4000h Base Block 15 Base Block 14 Base Block 13 Base Block 12 Base Block 11 Base Block 10 Base Block 9 Base Block 8 Base Block 0 0000h Base Block ...

Page 42: ...n A a n E a n 12 a n 16 a n 1A a n 1E a n 3 a n 7 a n B a n F a n 13 a n 17 a n 1B a n 1F 8 dots 2 256 Colors x 1 Palette There is 1 dot specified per address Thus the amount of data for each basic character is 40H x 8 bits a n 4 a n C a n 14 a n 1C a n 24 a n 2C a n 34 a n 3C a n 5 a n D a n 15 a n 1D a n 25 a n 2D a n 35 a n 3D a n 6 a n E a n 16 a n 1E a n 26 a n 2E a n 36 a n 3E a n 7 a n F a ...

Page 43: ...rmats 1 Text BG Screen A text BG screen consists of 2 bytes of screen data per basic character 1 024 character types can be specified 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Character name Horizontal flip flag Vertical flip flag Color Palette With 16 colors x 16 palettes 0 15 With 256 colors x 1 palette disabled d15 12 Color Palette If the color mode specification in the BG control registe...

Page 44: ...rea of VRAM Consequently in managing VRAM the following points deserve particular attention 1 There are 2 formats for BG character data defined by 16 and 256 colors and these can be used together 2 The BG character data base block can be selected from among 4 blocks BG control register 3 The BG screen data base block can be selected from among 32 blocks BG control register 4 The screen size amount...

Page 45: ...CH 0DCH 4FCH 7FAH 7FCH 03EH 0BEH 07EH 0DEH 4FEH 7BEH 7FEH 07AH 0DAH 0BAH 4FAH 240 dots 30 blocks 160 dots 20 blocks 256 dots 32 blocks 256 dots 32 blocks 780H 782H 784H 788H 786H 7BAH 7BCH 1 2 Virtual Screen Size of 512 x 256 Dots LCD Display Area 000 H 002 H 004 H 006 H 040 H 042 H 044 H 080 H 082 H 084 H 086 H 800 H 03A H 046 H 83E H 4C0 H 4C2 H 4C4 H 4C6 H 7C8 H 7C0 H 7C2 H 7C4 H 7C6 H 07C H 03...

Page 46: ...s 64 blocks 7C0H 800H 7C2H 7C4H 03CH 7FEH 83EH 4FCH 4FEH 4FAH 07CH 03EH 07EH 7FCH 1 4 Virtual Screen Size of 512 x 512 Dots LCD display area 000H 002H 004H 040H 042H 044H 800H 07AH 4C0H 4C2H 4C4H 7FEH 7C0H 7C2H 7C4H 7FCH 4FAH 1000H 256 dots 32 blocks 512 dots 64 blocks 256 dots 32 blocks 512 dots 64 blocks 256 dots 32 blocks 256 dots 32 blocks 83EH 03AH 03CH 03EH 07CH 07EH 4FCH 4FEH FC0H 103EH 180...

Page 47: ...blocks 128 dots 16 blocks 240 dots 30 blocks 160 dots 20 blocks 2 2 Virtual Screen Size of 256 x 256 Dots LCD display area 000H 001H 002H 003H 020H 041H 042H 084H 040H 081H 082H 083H 004H 044H 01DH 043H 060H 0C1H 0C2H 0C3H 264H 260H 261H 262H 263H 0C4H 280H 281H 282H 283H 284H 3E4H 3E0H 3E1H 3E2H 3E3H 03E H 01EH 05EH 06EH 27EH 29DH 29EH 3FDH 3FEH 01FH 05FH 03FH 06FH 29FH 27FH 3DFH 3FFH 03DH 06DH 0...

Page 48: ... FFFH 05DH 0DDH 09DH 4DDH 240 dots 30 blocks 160 dots 20 blocks 512 dots 64 blocks 512 dots 64 blocks F80H F81H F82H F84H F83H F9DH F9EH FBEH 2 4 Virtual Screen Size of 1024 x 1024 Dots 000H 001H 002H 003H 080H 081H 082H 104H 100H 101H 102H 103H 004H 084H 01DH 083H 180H 181H 182H 183H 984H 980H 981H 982H 983H 184H A00H A01H A02H A03H A04H 3F84H 3F80H 3F81H 3F82H 3F83H 09EH 01EH 11EH 19EH 99EH A1DH...

Page 49: ...tance moved in directionx same line 1 α cos θ dy distance moved in direction y same line 1 β sin θ dmx distance moved in direction x next line 1 α sin θ dmy distance moved in direction y next line 1 β cos θ α Magnification along x axis β Magnification along y axis θ θ dx dy dmy dmx Rotation center coordinate 0 0 y x Origin 0 0 Coordinate before rotation 1 1 y x Coordinate after rotation 2 2 y x BG...

Page 50: ...15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 BG2Y_H BG3Y_H 02Eh 03Eh 0000h W Address Register AttributesInitial Value Y coordinate of reference starting point rotation scaling results Y coordinate of reference starting point rotation scaling results X coordinate of reference starting point rotation scaling results Registers for Setting the Direction Parameters of BG Data 15 14 13 12 11 10 09 08...

Page 51: ... circuit sums the increases in the x direction dx dy in relation to the BG data reference starting point set in the above registers and calculates the x coordinate 3 When the line is advanced the increases in the y direction dmx dmy are summed in relation to the reference starting point and the coordinate of the rendering starting point for the next line is calculated The processing in step 2 is t...

Page 52: ... BG and Bitmap Mode BG set the BG Reference Starting Point See 6 1 7 BG Rotation and Scaling Features Offset Settings Registers H offset 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 BG0HOFS BG1HOFS BG2HOFS BG3HOFS 010h 014h 018h 01Ch 0000h W Address Register AttributesInitial Value V offset 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 BG0VOFS BG1VOFS BG2VOFS BG3VOFS 012h 016h 01Ah 01Eh 0000h...

Page 53: ...ol the BG2CNT Register is used 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 BG2CNT 00Ch 0000h R W Address Register Attributes Initial Value Priority Specification 00 1st priority 01 2nd priority 10 3rd priority 11 4th priority 0 0 Mosaic 0 Disable 1 Enable BG2CNT d06 Mosaic This controls the ON OFF of mosaic processing for BG2 When ON the settings for the Mosaic Size Register MOSAIC are referen...

Page 54: ...ly the amount of pixel data corresponding to the size of the display screen can be stored in VRAM Available bitmap modes allow the simultaneous display of 32 768 colors BG modes 3 and 5 and the display of 256 of the 32 768 colors BG mode 4 The format of the data in the frame buffer differs between the modes as described below 1 32 768 Color Simultaneous Display Format BG Modes 3 and 5 Palette RAM ...

Page 55: ...his mode is used mainly for still images However it enables 32 768 colors to be displayed simultaneously over the full screen 0 1 2 3 4 236 237 238 239 0 0h 2h 4h 6h 8h 1D8h 1Dah 1DCh 1DEh 1 1E0h 1E2h 1E4h 1E6h 1E8h 3B8h 3Bah 3BCh 3BEh 2 3C0h 3C2h 3C4h 3C6h 3C8h 598h 59Ah 59Ch 59Eh 3 5A0h 5A2h 5A4h 5A6h 5A8h 778h 77Ah 77Ch 77Eh 4 780h 782h 784h 786h 788h 958h 95Ah 95Ch 95Eh 156 12480h 12482h 12484...

Page 56: ...32Ch 932Dh 932Eh 932Fh 157 9330h 9331h 9332h 9333h 9334h 941Ch 941Dh 941Eh 941Fh 158 9420h 9421h 9422h 9423h 9424h 950Ch 950Dh 950Eh 950Fh 159 9510h 9511h 9512h 9513h 9514h 95FCh 95FDh 95FEh 95FFh VRAM address 06000000h 2 Frame 1 0 1 2 3 4 236 237 238 239 0 A000h A001h A002h A003h A004h A0ECh A0EDh A0EEh A0EFh 1 A0F0h A0F1h A0F2h A0F3h A0F4h A1DCh A1DDh A1DEh A1DFh 2 A1E0h A1E1h A1E2h A1E3h A1E4h ...

Page 57: ...Eh 125 9C40h 9C42h 9C44h 9C46h 9C48h 9D78h 9D7Ah 9D7Ch 9D7Eh 126 9D80h 9D82h 9D84h 9D86h 9D88h 9EB8h 9EBAh 9EBCh 9EBEh 127 9EC0h 9EC2h 9EC4h 9EC6h 9EC8h 9FF8h 9FFAh 9FFCh 9FFEh VRAM Address 06000000h 2 Frame 1 0 1 2 3 4 156 157 158 159 0 A000h A002h A004h A006h A008h A138h A13Ah A13Ch A13Eh 1 A140h A142h A144h A146h A148h A298h A29Ah A29Ch A29Eh 2 A2A0h A2A2h A2A4h A2A6h A2A8h A3B8h A3BAh A3BCh A3...

Page 58: ...umber per line 128 8x8 dot conversion Color special effects HV flip semi transparency mosaic priority specification OBJ windows OBJ Display Capability on a Single Line The single line OBJ display capability shown in the table above is the capability at maximum efficiency When the displayed OBJ are arranged continuously from the start of OAM you can calculate the OBJ display capability on a single ...

Page 59: ...ndering Cycles Number of OBJ displayable on single line OBJ H Size Normal OBJ Rotation Scaling OBJ Normal OBJ Rotation Scaling OBJ 8 8 26 128 47 16 16 42 76 29 32 32 74 38 16 64 64 138 19 8 128 double the size of 64 X 266 X 4 If the number for non displayed outside of the screen OBJ in the OAM is lower than that for displayed OBJ the bigger the non displayed OBJ s size is the less efficient the re...

Page 60: ... the 2 dimensional mapping mode shown in the following figure 000H 001H 002H 003H 020H 021H 022H 044H 040H 041H 042H 043H 004H 024H 025H 005H 023H 045H 060H 061H 062H 063H 080H 081H 082H 0A4H 0A0H 0A1H 0A2 H 0A3H 064H 084H 085H 065H 083H 0A5H 0C0H 0C1H 0C2H 0C3H 0E0H 0E1H 0E2H 104H 100H 101H 102H 103H 0C4H 0E4H 0E5H 0C5H 0E3H 105H 120H 121H 122H 123H 140H 141H 142H 164H 160H 161H 162H 163H 124H 14...

Page 61: ...ta that comprise a character are stored in contiguous addresses 64 x 64 dot character 16 color x 16 palette format 16 x 16 dot character 256 colors x 1 palette format 8 x 8 dot character 16 colors x 16 palette format 000h 100h 900h 0FFh 8FFh 16 x 32 dot character 256 colors x 1 palette format 91Fh 920h b20h n n 1 n 2 n 3 n 4 n 5 n 6 n 7 n 8 n 9 n 10 n 11 n 12 n 13 n 14 n 15 n 16 n 17 n 18 n 19 n 2...

Page 62: ...pping OBJ attributes occupying 48 bits x 128 OBJs can be written to OAM In addition when rotation scaling are performed for an OBJ a total of 32 instances of rotation scaling parameter combinations PA PB PC and PD can be written to OAM as shown in the following figure OAM Rotation Scaling Parameter PA 0 Rotation Scaling Parameter PB 0 OBJ0 OBJ1 Rotation Scaling Parameter PD 31 07000000h 070003FEh ...

Page 63: ...ow 11 Prohibited code OBJ Shape 00 Square 01 Horizontal Rectangle 10 Vertical Rectangle 11 Prohibited Code OBJ Mosaic 0 OFF 1 ON Color Mode 0 16 colors x 16 palettes 1 256 colors x 1 palette d15 14 OBJ Shape Selects the OBJ Character Shape Square Horizontal Rectangle or Vertical Rectangle 11 is a prohibited code Please also refer to OBJ size specification for OBJ Attribute 1 d13 Color Mode Flag Sp...

Page 64: ...ormed For information on color special effects see 9 Color Special Effects OBJs for which an OBJ window specification is used are not displayed as normal OBJs dots with non zero character data are used as the OBJ window d09 Rotation Scaling Double Size Flag OBJs are limited in size by the OBJ field 8x8 64x64 dots and the character data may surpass the boundaries of this field when rotated This pro...

Page 65: ...isplay Double Size object field Individual Control of OBJ display It is possible to control the ON and OFF functions of the OBJ display individually by setting in the combination of this double size flag and the rotation scaling flag of d08 In case of double size flag rotation scaling flag 1 0 OBJ is not displayed but is displayed in other cases d08 Rotation Scaling Flag Allows rotation processing...

Page 66: ... the display screen to be specified Cautions 160 dots in total 0 159 are inside the display screen and 96 dots in total 160 255 are outside the display screen virtual screen When the vertical size displays a 64 dot OBJ by a double size of character the size is 128 dots exceeding the vertical 96 dots for the virtual screen Therefore in the range of Y coordinate values of 129 159 the lower part of O...

Page 67: ...BJ Size OBJ Shape 00 01 10 11 Prohibited Code Square Horizontal Rectangle Vertical Rectangle d13 d12 Vertical and Horizontal Flip Flags Allows the OBJ to be flipped horizontally and vertically A normal display is produced by a setting of 0 and a flip display by a setting of 1 When the rotation scaling flag d08 of OBJ Attribute 0 is enabled these bits also can be used as the high order bits of the ...

Page 68: ...at is specified in the color mode bit these bits specify 1 of the 16 palettes to apply to the character data When 256 colors x 1 palette format is specified in the color mode bit these bits are disabled d11 10 Priority Relative to BG Specifies the display priority of the OBJ relative to BG For information on priority see section 6 4 Display Priority of OBJ and BG d09 00 Character Name Writes the n...

Page 69: ...dering Functions 1999 2001 Nintendo of America Inc 69 D C N AGB 06 0001 002B4 BG Mode is 3 5 Bitmap Mode OBJ character data RAM is halved to 16 KB so character name numbers 0 511 are disabled and numbers 512 and greater are used ...

Page 70: ...n next line 1 α sin θ dmy distance moved in y direction next line 1 β cos θ x axis y axis α Magnification along x axis β Magnification along y axis OBJ Character Data θ θ dx dy dmy dmx OBJ Center Horizontal Line Before Rotation Object Field Double Size Object Field When an OBJ is displayed the OBJ character data are referenced horizontally beginning from the left uppermost position Rotation displa...

Page 71: ...g the next line The processing in step 2 above is then performed Rotation Scaling Parameters Specifies the direction of character data reference in OBJ rotation scaling processing The values set for PA PB PC and PD are signed fixed point numbers 8 bit fractional portion 7 bit integer portion 1 bit sign for a total of 16 bits These 4 parameters are used together as a single group which can be place...

Page 72: ...ber is given priority 3 Priority Among BGs and OBJs The priority of each OBJ in relation to the BG can be set to 4 levels Please refer to the following figure Cautions for priority When orders of OBJ number and OBJ priority are reversed the display is not right if BG is between the OBJs Please be cautious not to let this situation occur Examples of when display is not right OBJ No 0 OBJ priority 2...

Page 73: ...tes come in the following two forms 1 16 Colors x 16 Palettes This mode provides 16 color palettes each consisting of 16 colors Color 0 for OBJ and BG palettes is forcibly allocated to transparent color specification disabled 2 256 Colors x 1 Palette This mode allocates all 256 of its colors to 1 palette Color data are represented by 15 bits 5 for Red 5 for Green and 5 for Blue Colors can be selec...

Page 74: ...and BGs use separate palettes The size of palette RAM is large enough 512 bytes to hold data 16 bit for up to 256 colors of 32 768 that can be specified The memory map of the OBJ and BG palettes is shown in the follow figure OBJ Palette RAM 512 bytes BG Palette RAM 512 bytes Palette RAM 05000000h 05000200h 050001FFh 050003FFh ...

Page 75: ... referenced as shown in the following figure Palette 0 Color 0 Color 1 Color 2 Color 3 Color 4 Color 255 Color 254 Color 253 Color 252 Palette RAM Color 0 Color 1 Color 2 Color 3 Color 13 Color 14 Color 15 Palette 0 Palette 1 Palette 2 Palette 3 Palette 4 Palette 5 Palette 6 Palette 7 Palette 8 Palette 9 Palette 10 Palette 11 Palette 12 Palette 13 Palette 14 Palette 15 Palette RAM 16 Colors x 16 P...

Page 76: ...tes 1999 2001 Nintendo of America Inc 76 D C N AGB 06 0001 002B4 7 3 Color Data Format Allows 1 of 32 768 colors to be specified 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Red Green Blue B4 B3 B2 B1 B0 G4 G3 G2 G1 G0 R4 R3 R2 R1 R0 ...

Page 77: ...oordinates of a rectangular area These settings specify the window s position and size When a non rectangular window is displayed the values of these registers are updated during H blanking intervals Window Display Example Window 0 has a higher display priority than Window 1 Window 1 Window 0 Display Screen 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 WIN0H WIN1H 040h 042h 0000h W Address Regis...

Page 78: ...rol of Inside of Window The WININ register controls display of the area inside windows 0 and 1 The high order bits d13 8 control Window 1 while the low order bits d5 0 control Window 0 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 WININ 048h 0000h R W Address Register Attributes Initial Value OBJ BG3 BG2BG1 BG0 OBJ BG3BG2 BG1 BG0 Window 1 Window 0 Color Special Effects Flag 0 Disable color speci...

Page 79: ...OBJ Window Windows 0 and 1 Attributes Initial Value Display Flag 0 No display 1 Display Display Flag 0 No display 1 Display Color Special Effects Flag 0 Disable color special effects 1 Enable color special effects Color Special Effects Flag 0 Disable color special effects 1 Enable color special effects WININ d12 08 d04 00 WINOUT d12 08 d04 00 Display Flags Turns display of the OBJ and BG 3 0 on an...

Page 80: ...tic operations on 1 selected surface and implements processing for 16 levels of brightness 9 1 Selection of Color Special Effects The types of color special effects and the target pixels are determined by the BLDCNT register 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 BLDCNT 050h 0000h R W Address Register Attributes Initial Value OBJ BG3BG2 BG1 BG0 BD OBJBG3 BG2 BG1BG0 BD 1st Target Pixel 2nd...

Page 81: ...he 1 st target screen should be turned off d05 0 When OBJ 1 for the 1 st target pixel processing is executed for all OBJs regardless of the OBJ type When OBJ 0 processing is executed only if the OBJ is semi transparent 1 0 Brightness Increase Gradually increases brightness for 1 st target screen The entire screen can gradually be made whiter by setting all bits of the specification for the 1st tar...

Page 82: ...al Value Address Register Color Special Effects Coefficient EVY Coefficients used in α blending processing are specified in EVA and EVB of the BLDALPHA register The coefficient used in processing brightness changes is specified in EVY of the BLDY register The values of EVA EVB and EVY are numbers less than 1 and are obtained by multiplying 1 16 by an integer EVA EVB EVY Coeff EVA EVB EVY Coeff 0 0...

Page 83: ... R EVA 2nd pixel color R EVB Display color G 1st pixel color G EVA 2nd pixel color G EVB Display color B 1st pixel color B EVA 2nd pixel color B EVB 2 Brightness Increase Operations Display color R 1st pixel R 31 1st pixel R EVY Display color G 1st pixel G 63 1st pixel G EVY Display color B 1st pixel B 31 1st pixel B EVY 3 Brightness Decrease Operations Display color R 1st pixel R 1st pixel R EVY ...

Page 84: ...3 Sound 2 Allows generation of rectangular waveforms with envelope functions 4 Sound 3 Allows playback of any waveform recorded in waveform RAM Waveform RAM in AGB has double the capacity of that in CGB 5 Sound 4 Can generate white noise with the envelope function The synthesis ratio of sounds 1 4 to direct sound can be specified 10 1 Sound Block Diagram DMA1 FIFO A 8 Words Sound 1 Sound 2 Sound 3...

Page 85: ...ound Data 3 Sound Data 2 Address Register Attributes Initial Value Sound Data All sounds are PWM modulated refer to 10 8 Sound PWM Control at the final portion of the Sound Circuit Therefore if you match the 8 bit audio data sampling frequency and the timer settings with the PWM modulation sampling frequency a clean sound can be produced The following operations are repeated for direct sound Prepa...

Page 86: ...ount up the audio data are passed from the FIFO to the sound circuit 2 If 4 words of data remain in the FIFO as the transfer count progresses the FIFOs for direct sounds A and B output a data transfer request to the specified DMA channel 3 If the DMA channel receiving the request is in sound FIFO transfer mode 4 words of data are provided to the sound FIFO the DMA WORD COUNT is ignored The precedi...

Page 87: ...s Register Attributes Intial Value NR10 No of sweep shifts 0 7 Sweep Increase Decrease 0 Addition increase frequency 1 Decrease decrease frequency Sweep time SOUND1CNT_L d06 04 Sweep Time These bits specify the interval for frequency change Setting Sweep Time 000 Sweep OFF 001 1 f128 7 8 ms 010 2 f128 15 6 ms 011 3 f128 23 4 ms 100 4 f128 31 3 ms 101 5 f128 39 1 ms 110 6 f128 46 9 ms 111 7 f128 54...

Page 88: ...pped and the Sound 1 ON flag bit 0 of NR52 is reset With subtraction if the subtrahend is less than 0 the pre subtraction value is used However if the specified setting is 0 shifting does not occur and the frequency is unchanged 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 SOUND1 CNT_H 062h 0000h R W Address Register Attributes Initial Value NR11 NR12 Sound Length 0 63 Waveform duty cycle Envel...

Page 89: ... of 1 step steptime is determined by the following formula steptime n 1 64 sec When n 0 the envelope function is turned off SOUND1CNT_H d07 06 Waveform Duty Cycle Specifies the proportion of amplitude peaks for the waveform 00 Setting Duty Cycle Waveform 01 10 11 12 5 25 0 50 0 75 0 SOUND1CNT_H d05 00 Sound Length With st signifying the sound length the length of the output sound is determined by ...

Page 90: ...nge of frequencies is 64 to 131 1 KHz Sound 1 Usage Notes 1 When the sweep function is not used the sweep time should be set to 0 and the sweep increase decrease flag should be set to 1 2 If sweep increase decrease flag of NR10 is set to 0 the number of sweep shifts set to a non zero value and sweep OFF mode is set sound production may be stopped 3 When a value is written to the envelope register ...

Page 91: ...ope Increase Decrease 0 Attenuate 1 Amplify No of Envelope Steps 0 7 SOUND2CNT_L d15 12 Envelope Initial Value Allows specification of any one of 16 levels ranging from maximum to mute SOUND2CNT_L d11 Envelope Increase Decrease Specifies whether volume will increase or decrease SOUND2CNT_L d10 08 Number of Envelope Steps Sets the length of 1 step of envelope amplification or attenuation With n sig...

Page 92: ...or the time specified in the sound length data of NR21 When sound output ends the Sound 2 ON flag of NR52 is reset SOUND2CNT_H d10 00 Frequency Data With fdat signifying the frequency data the output frequency is determined by the following formula f fdat Hz 4194304 4 2 2048 3 Thus the frequency range that can be specified is 64 to 131 1 KHz Sound 2 Usage Note 1 When a value is written to the enve...

Page 93: ...iation Spec 0 32 Steps 1 64 Steps Waveform RAM Bank Specification 0 Bank 0 1 Bank 1 Sound Output Flag 0 Stop Output 1 Output Attributes Initial Value Address Register SOUND3CNT_L d07 Sound Output Flag Sound output stops when 0 sound output occurs when 1 SOUND3CNT_L d06 Waveform RAM Bank Specification Two banks of waveform RAM are provided banks 0 and 1 The Sound 3 circuit plays the waveform data i...

Page 94: ...utput level selections are as shown in the following table Setting Output Level 00 Mute 01 Outputs the waveform RAM data unmodified 10 Outputs the waveform RAM data with the contents right shifted 1 bit 1 2 11 Outputs the waveform RAM data with the contents right shifted 2 bits 1 4 SOUND3CNT_H d07 00 Sound Length The sound length time is determined by the following formula with st signifying the s...

Page 95: ...f is determined by the following formula Hz fdat f 2048 2 4 4194304 3 Thus the specifiable range of frequencies is 64 to 131 1 KHz Sound 3 Usage Note 1 When changing the frequency during Sound 3 output do not set the initialization flag The contents of waveform RAM may be corrupted With sounds 1 2 and 4 the initialization flag can be set without problems 2 For sound 3 if you change the frequency w...

Page 96: ... 01 00 WAVE_ RAM1_L 094h R W Step 9 Step 8 Step 11 Step 10 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 WAVE_ RAM1_H 096h R W Step 13 Step 12 Step 15 Step 14 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 WAVE_ RAM2_L 098h R W Step 17 Step 16 Step 19 Step 18 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 WAVE_ RAM2_H 09Ah R W Step 21 Step 20 Step 23 Step 22 15 14 13 12 11 10 09 08 07 06 05 04...

Page 97: ...ps 0 7 Envelope Initial Value SOUND4CNT_L d15 12 Envelope Initial Value Allows specification of any of 16 levels ranging from maximum to mute SOUND4CNT_L d11 Envelope Increase Decrease Specifies whether to increase or decrease the volume SOUND4CNT_L d10 08 Number of Envelope Steps Sets the length of each step of envelope amplification or attenuation With n the specified value the length of 1 step ...

Page 98: ...ation Flag A setting of 1 causes Sound 4 to be restarted SOUND4CNT_H d14 Sound Length Continuous sound output with 0 with 1 sound output only for the time specified in the sound length data of NR41 When sound output ends the Sound 4 ON flag of NR52 is reset SOUND4CNT_H d07 04 Polynomial Counter Shift Clock Frequency Selection With n signifying the specified value the shift clock frequency shiftfre...

Page 99: ... 194304 MHz selection is as shown in the following table Setting Dividing Ratio Frequency 000 fx1 23 x2 001 fx1 23 x1 010 fx1 23 x 1 2 011 fx1 23 x 1 3 100 fx1 23 x 1 4 101 fx1 23 x 1 5 110 fx1 23 x 1 6 111 fx1 23 x 1 7 Sound 4 Usage Note When a value is written to the envelope register sound output becomes unstable before the initialization flag is set Therefore set initialization flag immediatel...

Page 100: ... Output Level 0 7 Sound 1 R Output Flag Sound 2 R Output Flag Sound 3 R Output Flag Sound 4 R Output Flag Sound 1 L Output Flag Sound 2 L Output Flag Sound 3 L Output Flag Sound 4 L Output Flag SOUNDCNT_L d15 12 L Output Flag for each Sound No output of that sound to L when 0 Output of that sound to L when 1 SOUNDCNT_L d11 08 R Output Flag for each Sound No output of that sound to R when 0 Output ...

Page 101: ...ounds Operation Flag The master flag that controls whether sound functions as a whole are operating A setting of 0 halts all sound functions including direct sound producing a mute state In this situation the contents of all the Sound mode registers are reset Always set all the sound operation flags to 1 when setting each sound mode register You cannot set each sound mode register when all the sou...

Page 102: ... Output of Direct Sound A 0 No output to R 1 Output to R L Output of Direct Sound A 0 No output to L 1 Output to L Direct Sound FIFO A Clear and Sequencer Reset Timer Selection for Direct Sound A 0 Timer 0 1 Timer 1 R Output of Direct Sound B 0 No output to R 1 Output to R L Output of Direct Sound B 0 No output to L 1 Output to L Direct Sound FIFO B Clear and Sequencer Reset Timer Selection for Di...

Page 103: ... Each Direct Sound Controls the output to L for each direct sound A setting of 0 results in no output to L a setting of 1 causes output to L SOUNDCNT_H d12 d08 R Output for Each Direct Sound Controls the output to R for each direct sound A setting of 0 results in no output to R a setting of 1 causes output to R SOUNDCNT_H d03 d02 Output Ratio for Each Direct Sound Selects the output level for each...

Page 104: ...e resolution and sampling cycle frequency during PWM modulation The DMG compatible sound is input at 4 bits 130 93KHz so in order to have accurate modulation the sampling frequency must be set high Direct sound will arbitrarily decide the sampling frequency based on the timer setting By using the sampling frequencies listed in the table below an accurate modulation can be done Thus in order to inc...

Page 105: ...AGB Programming Manual Sound 1999 2001 Nintendo of America Inc 105 D C N AGB 06 0001 002B4 SOUNDBIAS d09 00 Bias Level This is used by system ROM Please do not change this value as it may cause errors ...

Page 106: ...tributes Initial Value 2 Timer Control Count up Timing 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 TM0CNT_H TM1CNT_H TM2CNT_H TM3CNT_H 102h 106h 10Ah 10Eh 0000h R W Timer Operation Flag 0 Disable 1 Enable Interrupt Request Enable Flag 0 Disable 1 Enable Prescalar Selection Address Register Attributes Initial Value TM CNT_H d07 Timer Operation Flag Starts and stops the timer A setting of 0 stop...

Page 107: ...he prescalar specification This mode is suitable for purposes such as time measurement over relatively long periods The count up timing specification is disabled for Timer 0 which counts up in accordance with the prescalar specification TM CNT_H d01 00 Prescalar Selection Allows selection of a prescalar based on the system clock 16 78MHz Setting Prescalar Count Up Interval 00 System clock 59 595 n...

Page 108: ... DMA channels Thus it is used for reliable processing over a limited period as is required for purposes such as horizontal blanking DMA Ø DMA 1 and DMA 2 These are used for direct sound functions which require relatively high priority or for general purpose transfers Ø DMA 3 This is used for the most general types of transfers Perform the following settings when using DMA 1 Specify the transfer so...

Page 109: ...on Address Specifies the destination address using 27 bits The area 00000000h 07FFFFFFh internal memory area of main unit can be specified 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 DMA0 DAD_L 0B4h 0000h W Address Register Attributes Initial Value 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 DMA0 DAD_H 0B6h 0000h W Address Register Attributes Initial Value 3 Word Count Specifies the number...

Page 110: ...nt after Transfer 01 Decrement after Transfer 10 Fixed 11 Prohibited Code DMA Start Timing 00 Start Immediately 01 Start in a V blank Interval 10 Start in an H blank Interval 11 Prohibited Code Interrupt Request Enable Flag 0 Disable 1 Enable DMA Enable Flag 0 OFF 1 ON DMA0CNT_H d15 DMA Enable Flag A setting of 0 disables DMA A setting of 1 enables DMA and after the transfer is completed the sourc...

Page 111: ...nking interval approximately 16 212 µs If this accompanies OAM access the H blanking interval must first be freed of OBJ display hardware processing periods See 5 Image System 11 Prohibited Code DMA0CNT_H d10 DMA Transfer Type Sets the bit length of the transfer data With a setting of 0 the data are transferred by DMA in 16 bit half word units With a setting of 1 the data are transferred by DMA in...

Page 112: ...01 causes a decrement A setting of 10 causes it to be fixed 11 is a prohibited code DMA0CNT_H d07 Destination Address Control Flag Control of the destination address is specified after each DMA transfer A setting of 00 causes an increment A setting of 01 causes a decrement A setting of 10 causes it to be fixed A setting of 11 causes an increment and after all transfers end a reload The setting is ...

Page 113: ...ation address using 27 bits The area 00000000h 07FFFFFFh internal memory area of main unit can be specified 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 DMA1DAD_L DMA2DAD_L 0C0h 0CCh 0000h W 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 0C2h 0CEh 0000h W DMA1DAD_H DMA2DAD_H Address Register Attributes Initial Value Address Register Attributes Initial Value 3 Word Count Specifies the number of...

Page 114: ...r 01 Decrement after Transfer 10 Fixed 11 Prohibited Code DMA Start Timing 00 Start Immediately 01 Start in a V blank Interval 10 Start in an H blank Interval 11 Prohibited Code Interrupt Request Enable Flag 0 Disable 1 Enable DMA Enable Flag 0 OFF 1 ON 0D2h DMA2CNT_H DMA 1 2 CNT_H d15 DMA Enable Flag A setting of 0 disables the DMA function A setting of 1 enables DMA and after the transfer is com...

Page 115: ...erval approximately 4 993 ms 10 Start During a H blanking interval Starts at the beginning of a H blanking interval approximately 16 212 µs If this accompanies OAM access the H blanking interval must first be freed of OBJ display hardware processing periods See Chapter 5 Image System 11 Start When Request Generated by Direct Sound FIFO Starts when a request is received form direct sound FIFO Speci...

Page 116: ... CNT_H d08 Source Address Control Flag Control of the source address is specified after each DMA transfer A setting of 00 causes an increment A setting of 01 causes a decrement A setting of 10 causes it to be fixed 11 is a prohibited code When the Game Pak Bus has been set to the source address make sure you select increment DMA 1 2 CNT_H d07 Destination Address Control Flag Control of the destina...

Page 117: ...ination Address Specifies the destination address using 28 bits The area 00000000h 0FFFFFFFh internal memory area of main unit and Game Pak memory area can be specified 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 DMA3DAD_L 0D8h 0000h W Address Register Attributes Initial Value 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 DMA3DAD_H 0DAh 0000h W Address Register Attributes Initial Value 3 Wor...

Page 118: ...sfer 10 Fixed 11 Prohibited Code DMA Start Timing 00 Start Immediately 01 Start in a V blank Interval 10 Start in an H blank Interval 11 Synchronize with display and start Interrupt Request Enable Flag 0 Disable 1 Enable DMA Enable Flag 0 OFF 1 ON Game Pak Data Request Transfer Flag 0 Disable Normal 1 Enable DMA3CNT_H d15 DMA Enable Flag A setting of 0 disables DMA A setting of 1 enables DMA and a...

Page 119: ...e beginning of a H blanking interval approximately 16 212 µs If this accompanies OAM access the H blanking interval must first be freed of OBJ display hardware processing periods See 5 Image System 11 Synchronize with display and start Synchronize with start of H Line rendering during a display interval and start DMA3CNT_H d11 Game Pak Data Request Transfer Flag Should normally be set to 0 When se...

Page 120: ...Game Pak data request mode do not use the repeat function DMA3CNT_H d08 Source Address Control Flag Control of the source address is specified after each DMA transfer A setting of 00 causes an increment A setting of 01 causes a decrement A setting of 10 causes it to be fixed 11 is a prohibited code When the Game Pak Bus has been set to the source address make sure you select increment DMA3CNT_H d0...

Page 121: ...able flag to 1 after making the above settings If the DMA enable flag is 1 when the V count value is 162 DMA transfers will be executed in the next frame Synchronizing with the horizontal line DMA which transfers the word count data per horizontal line will be executed 160 times from line 2 to line 161 Data is always DMA transferred to the frame buffer address located 2 horizontal lines before the...

Page 122: ...locks or more between the DMA start trigger and the timing to clear the DMA enabled flag by the CPU For example it is possible to stop the DMA safely by clearing an enabled flag before the next start trigger is sent by using an interrupt that occurs at the end of the DMA When this method cannot be used stop the DMA as shown below 2 1 How to stop DMA repeat in H blank and V blank mode DMA is not in...

Page 123: ...control bits No change However when the value of the DMA word count register is already set to 0004h the procedure is executed by writing in 16 bit width to the DMA control register It is possible to disable the next repeated DMA by setting the DMA to start immediately however Direct Sound FIFO Transfer mode will be cancelled so that the value of the Word count register will be used Therefore the ...

Page 124: ...ollowing settings in the 16 bit width to the DMA control register and stop the DMA DMA enabled flag 0 Disabled DMA start timing 00 DMA transfer type 1 DMA repeat 0 Destination address control flag 10 Other control bits No change Note Please note that the DMA may be started one extra time due to procedure 1 above ...

Page 125: ...ay communication due to cable connection of multi play communication Due to differences in voltage communication with DMG MGB CGB is not possible Similarly communication with previous DMG MGB CGB compatible hardware pocket printer etc which connects to an extension connector is not possible 2 16 Bit Multi player Communication Function This multiple simultaneous communication function uses UART sys...

Page 126: ...unication function set flag of the communication control register RCNT 2 bit and the communication mode set flag of the serial communication control register SIOCNT 2 bit which are described later RCNT SIOCNT Communication Functions d15 d14 d13 d12 General Purpose 1 0 JOY Bus 1 1 8 Bit Serial 0 0 0 32 Bit Serial 0 0 1 16 Bit Serial 0 1 0 UART 0 1 1 any Do not change or reset a communication mode d...

Page 127: ...AGB 0x0040 If communication is not finished SIO interrupt does not occur after a certain period of time or if there is a communication error after retries enter another communication mode once and then re enter the communication mode once again By doing this the communication circuit will be reset Cautions for Communication Function For communication take into consideration a case in which unexpec...

Page 128: ...ock mode will output the shift clock from SC terminal SD terminal will become an input terminal with pull up In the case of a slave external clock mode SC terminal will become an input terminal with pull up SD terminal will go to LO output The set data will be left shifted by the falling of the shift clock and will be output from the SO terminal in order starting from the most significant bit The ...

Page 129: ...ttributes Initial Value 32 bit Normal Serial Communication Data Register 32 bit transfer mode uses 120h SIODATA32_L and 122h SIODATA32_H as data registers These data registers are used for 16 bit multi player communication also The most significant bit will be d15 in the register SIODATA32_H and the least significant bit will be d0 in the register SIODATA32_L 15 14 13 12 11 10 09 08 07 06 05 04 03...

Page 130: ...le flag receive Transfer Length Set Flag 0 8 bit Transfer 1 32 bit Transfer Start Bit 0 No Serial Transfer 1 Start Serial Transfer reset when finished Interrupt Request Enable Flag 0 Disable 1 Enable Transfer Enable Flag Send 0 Enable Transfer 1 Disable Transfer Internal Shift Clock Selection 0 256 KHz 1 2 MHz 0 SIOCNT d14 Interrupt Request Enable Flag If 0 is set an interrupt request will not be ...

Page 131: ...e SC terminal from another hardware unit SD terminal will go to LO output If 1 an internal clock is used as a shift clock master The internal clock is output from the SC terminal and SD terminal will be in the pull up input status Cautions for Normal Serial Communications The shift clock should be selected before the start bit of the SIOCNT register is set Extra shift operations may result if the ...

Page 132: ...2 D C N AGB 06 0001 002B4 Always set a communication speed at 256KHz when performing normal communication with the AGB Game Link cable Communication cannot be done properly at 2MHz Also please note it will be a one way communication due to cable connection of multi play communication ...

Page 133: ...r Special Hardware 2MHz for the frequency Set transfer data Communicate as the Master Select external clock with Register SIOCNT Set start flag for Register SIOCNT Is d02 in Register SIOCNT 0 Set 1 in d03 of Control Register SIOCNT Set 0 in d03 of Register SIOCNT Set Start Flag for Register SIOCNT and wait for external clock input Start Flag for Register SIOCNT is reset If the Interrrupt Request E...

Page 134: ... LO input to the SI terminal becomes the master The terminal that is HI input to the SI terminal becomes the slave If you set the start bit of Register SIOCNT of the master the data registers SIOMULTI0 SIOMULTI1 SIOMULTI2 and SIOMULTI3 of the master are initialized to FFFFh Additionally the SYNC signal LO level is output from the SC terminal At the same time the Start bit LO level is output from t...

Page 135: ...after the output of a 5 cycle HI interval of source oscillation and the transmission ends 1 After the master outputs its own Stop bit the next Start bit is not input after a certain period of time 2 After a Stop bit is received from the first or second slave a Start bit is not input after a certain period of time 3 A Stop bit is received from the third slave Once the transmission ends the received...

Page 136: ... 0 1 F 0 1 F Master Data Primary Slave Data Secondary Slave Data SD SC SI SO Set Communication Mode Input Input Output SD SI SO SC Sent to GND with Communication Cable Primary Slave Master HI LO View of Terminal Status 0 1 F 0 1 F 0 1 F Interrupt Request Interrupt Request Multi Player AGB Game Link cable Connecting Diagram Small Connector Large Connector ...

Page 137: ...e Second slave and Third slave are in SIOMULTI1 SIOMULTI2 and SIOMULTI3 respectively 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 SIO MULTI0 120h 0000h R W Address Register Attributes Initial Value Data 0 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 SIO MULTI1 122h 0000h R W Data 1 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 SIO MULTI2 124h 0000h R W Data 2 15 14 13 12 11 10 09 08 07 06 ...

Page 138: ...r 01 1st Slave 10 2nd Slave 11 3rd Slave Baud Rate 00 9600bps 01 38400bps 10 57600bps 11 115200bps SI Terminal SD Terminal SIOCNT d14 Interrupt Request Enable Flag When set to 0 no interrupt request is generated When set to 1 an interrupt request is generated upon the completion of multi player communication SIOCNT d07 Start Bit Busy Flag 1 Master d00 is 1 When set to 0 no data is transferred When...

Page 139: ...aming Error However communication continues even when an error occurs and invalid data is stored in SIOMULTI0 SIOMULTI3 Confirm error flags when communicating so there are no problems created in case of an incorrect cable connection SIOCNT d05 04 Multi player ID Flag When multi player communication ends an ID code will be stored which specifies the order that each particular machine was connected ...

Page 140: ...anual Communication Functions 1999 2001 Nintendo of America Inc 140 D C N AGB 06 0001 002B4 SIOCNT d01 d00 Baud Rate Sets the communication baud rate Setting Baud Rate 00 9600 bps 01 38400 bps 10 57600 bps 11 115200 bps ...

Page 141: ...ster Yes No Either there is an improper connection due to the Multi play Cable or the other machine is not in Multi play mode Do you want to abort communication No Yes No Output data and obtain data from all slaves Communication is started by the master and data is obtained from other machines Once this particular slave s number is reached data is output The multi play ID is stored in d05 d04 of R...

Page 142: ...nce data is written to the send data register data is sent after a Start bit 1 bit is sent from the SO terminal However when the CTS flag for the Control Register is set data can be sent only when there is a LO input to the SC terminal The Stop bit is a fixed 1 bit Data Register 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 SIO DATA8 12Ah 0000h R W Address Register Attributes Initial Value Relat...

Page 143: ... shift register are shifted out data is transferred from a send FIFO to a shift register immediately Please note when using this operation that data is immediately transferred to a shift register when the first data is written to the data register and the interrupt request condition is met as a send FIFO becomes empty Also when read data is read from a receive FIFO Only the lower 8 bits are valid ...

Page 144: ... Initial Value 1 1 Baud Rate 00 9600bps 01 38400bps 10 57600bps 11 115200bps Parity Control 0 Even parity 1 Odd parity Send Data Flag 0 Not Full 1 Full Receive Data Flag 0 Not Empty 1 Empty Error Flag 0 No Error 1 Error Data Length 0 7 bits 1 8 bits FIFO Enable Flag 0 Disable 1 Enable Send Enable Flag 0 Disable 1 Enable Receive Enable Flag 0 Disable 1 Enable CTS Flag 0 Send always possible 1 Send ...

Page 145: ...e receive FIFO is not full a LO is output from the SD terminal and a HI is output if it is reset You must first set the receive enable flag and send enable flag to 0 Disable before going from UART communication mode to a different communication mode SIOCNT d10 Send Enable Flag Controls the send enable disable You must first set the receive enable flag and send enable flag to 0 Disable before going...

Page 146: ... for the receive data Overrun Error When FIFO is invalid if the receive data is not empty SIOCNT d05 0 and next receive has ended detect stop bit Or when FIFO is valid if receive FIFO is full and next communication has ended detect stop bit SIOCNT d05 Receive Data Flag When set to 0 there is still data present When set to 1 it is empty SIOCNT d04 Send Data Flag When set to 0 it is not full After o...

Page 147: ... Manual Communication Functions 1999 2001 Nintendo of America Inc 147 D C N AGB 06 0001 002B4 SIOCNT d01 d00 Baud Rate Sets communication baud rate Setting Baud Rate 00 9600 bps 01 38400 bps 10 57600 bps 11 115200 bps ...

Page 148: ...4 Communication Function Set Flag When set to 00 or 01 operates as a serial communication 8 bit 16 bit serial communication multi player communication UART communication function terminal When set to 10 can be used as a general purpose input output terminal When set to 11 can be used as a JOY Bus communication terminal RCNT d08 Interrupt Request Enable Flag When general purpose input output is set...

Page 149: ... Nintendo of America Inc 149 D C N AGB 06 0001 002B4 RCNT d03 d00 Data Bit When the corresponding terminal is set for input the status HI LO of the terminal can be confirmed If the corresponding terminal is set for output the status of the set bit is output ...

Page 150: ...et Flag 1 1 JOY Bus Communication Control 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 JOYCNT 140h 0000h R W Address Register Attributes Initial Value Interrupt Request Enable Flag 0 Disable 1 Enable Device Reset Signal Receive Flag Receive Complete Flag Send Complete Flag JOYCNT d05 Interrupt Request Enable Flag When set to 0 an interrupt request is not generated When set to 1 an interrupt req...

Page 151: ...al Value Receive Upper Data Send Data Register 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 JOY_ TRANS_L 154h 0000h R W Address Register Attributes Initial Value Send Lower Data 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 JOY_ TRANS_H 156h 0000h R W Address Register Attributes Initial Value Send Upper Data Receive Status Register The lower 8 bits of the receive status register JOYSTAT is re...

Page 152: ...The transfer of the bit data for JOY Bus communication is done in units of bytes and in the order of MSB first Device Reset Command FFh Received The device reset signal receive flag for Register JOYCNT is set If the interrupt request enable flag for the same register is also set a JOY Bus interrupt request is generated Direction Order d7 d6 d5 d4 d3 d2 d1 d0 Remarks Receive 1 1 1 1 1 1 1 1 1 Comma...

Page 153: ... Register JOY_RECV_L 4 Lower 8 bits of receive data Register JOY_RECV_H Receive 5 Upper 8 bits of receive data Register JOY_RECV_H Receive Data Send 6 Lower 8 bits of Register JOYSTAT Communication Status AGB Data Read Command 14h Received 4 bytes of data stored in Register JOY_TRANS and the 1 byte communication status are sent and the send complete flag for Register JOYCNT is set Also if the inte...

Page 154: ...unication Functions 1999 2001 Nintendo of America Inc 154 D C N AGB 06 0001 002B4 13 6 AGB Game Link Cable When communicating between AGB units the AGB Game Link cable to be used will vary depending upon the type of Game Pak used ...

Page 155: ...02 01 00 KEY INPUT 130h 0000h R W A B L R SL ST Address Register Attributes Initial Value UP DWN LFT RT 14 2 Key Interrupt Control When an interrupt is performed for key input this register enables a target key combination or condition for the interrupt to be specified Interrupt Specification Flag 0 Not Specified 1 Specified 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 KEYCNT 132h 0000h R W A B...

Page 156: ...tions for buttons selected with the key interrupt specification flag can be selected as follows 1 Logical Addition OR Operation The conditions for interrupt request generation occur when there is input for any of the buttons specified as interrupts 2 Logical Multiplication AND Operation The conditions for interrupt request generation occur when there is simultaneous input for all of the keys speci...

Page 157: ...disabled When 1 the setting for interrupt enable register IE is enabled 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 IME 208h 0000h R W Adderess Register Attributes Initial Value Interrupt Master Enable Flag 2 Interrupt Enable Register With the interrupt enable register each hardware interrupt can be individually masked 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 IE 200h 0000h R W Address R...

Page 158: ...neral Purpose Communication JOY Bus Communication UART Communication Game Pak DREQ IREQ If a 1 is written to the bit which the interrupt request flag is set in that interrupt request flag can be reset Cautions regarding clearing IME and IE A corresponding interrupt could occur even while a command to clear IME or each flag of the IE register is being executed When clearing a flag of IE you need to...

Page 159: ...errupt To return control from the interrupt routine to the user program the instruction BX LR is used Interrupt Address Allocated Area Sound BufferAddress 03007FFC 03007FF4 LR_IRQ formerly PC R0 R1 R2 R3 R12 03007FF0 Interrupt Stack 6 words 1 time 03007FA0 User Stack 32 bit 03007F00 SP_irq SP_usr Interrupt Check Flag 03007FF8 Allocated Area 03007FE0 LR_SVC formerly IBPC R12 R11 System Call Stack 4...

Page 160: ...SP_irq 03007F00 IRQ Stack SVC Stack USR Stack 6 WORDS 03007FA0 03007F00 SP_svc 03007FE0 03007FA0 2 User interrupt processing is done you can reference the cause of the interrupt with the IF Register Also solve problems with a stack if necessary 3 Restore the registers total of 6 words saved to the Interrupt Stack and return to user main processing SP_usr SP_irq 03007F00 IRQ Stack SVC Stack USR Sta...

Page 161: ... SP_svc 03007FE0 03007FA0 2 User interrupt processing is done you can reference the cause of the interrupt with the IF Register à If multiple interrupts occur SPSR_irq will be overwritten so you must save before enabling IRQ SP_irq SP_usr IRQ Stack SVC Stack USR Stack 03007F00 6 WORDS 03007FA0 03007F00 SPSR_irq SP_svc 03007FE0 03007FA0 à The Stack problem is solved CPU mode is changed to user mode...

Page 162: ...1 002B4 à When an interrupt occurs Monitor ROMdoes the processing 1 again and loads each register to the interrupt stack LR_usr 6 WORDS SP_irq IRQ Stack SVC Stack USR Stack User Interrupt Processing 03007F00 6 WORDS 03007FA0 03007F00 SPSR_irq SP_svc 03007FE0 03007FA0 SP_usr àContinue processing 2 ...

Page 163: ...rrupt enable register IE is set for various interrupt requests of Key Cartridge and SIO general purpose communication mode only this mode will be canceled Remarks Canceling stop status requires a brief wait until the system clock stabilizes System Working Status in Stop Mode The working status of each block of the AGB system during a stop is shown in the following table Block Working Status AGB CP...

Page 164: ...m call SWI 2 instruction Halt AGB enters Halt status 2 Cancel Halt Mode Halt is canceled when the interrupt enable register IE s corresponding flag is set with any type of interrupt request System Working Status in Halt Mode The working status of each block of the AGB system during a semi stop is shown in the following table Block Working Status AGB CPU X Wait status resulting from wait signal LCD...

Page 165: ...LR_svc formerly PC to the system call stack with the monitor ROM SP_usr SP_irq 03007FA0 03007F00 03007F00 IRQ Stack SVC Stack USR Stack 4 WORDS 03007FE0 03007FA0 SP_svc 3 Switch from CPU mode to system mode Call the IRQ disable flag with monitor ROM The previous status will continue 4 Save the R2 and LR_usr registers to the user stack Other registers will be saved with each system call LR_usr SP_i...

Page 166: ...merica Inc 166 D C N AGB 06 0001 002B4 6 Return value to registers R0 R1 and R3 in cases where a system call provides a return value and then return to the user program SP_usr SP_irq 03007F00 IRQ Stack SVC Stack USR Stack 03007FA0 03007F00 SP_svc 03007FE0 03007FA0 ...

Page 167: ...registers will be saved with each system call LR_usr SP_irq SP_usr Save with each System Call 03007FA0 03007F00 03007F00 IRQ Stack SVC Stack Usr Stack 4 WORDS 03007FE0 03007FA0 R2 SP_svc 5 Interrupt occurs while executing system call LR_usr SP_usr 6 WORDS Save with each System Call 03007FA0 03007F00 03007F00 IRQ Stack SVC Stack USR Stack 4 WORDS 03007FE0 03007FA0 R2 SP_irq SP_svc 6 User interrupt ...

Page 168: ...ave with each System Call R2 6 WORDS 03007FA0 03007F00 03007F00 IRQ Stack SVC Stack USR Stack 4 WORDS 03007FE0 03007FA0 4 WORDS SP_usr SP_irq SP_svc LR_usr Save with each System Call R2 10 Complete processing with each system call LR_usr SP_svc SP_usr User Interrupt Processing 6 WORDS Save with each System Call 03007FA0 03007F00 03007F00 IRQ Stack SVC Stack USR Stack 4 WORDS 03007FE0 03007FA0 R2 4...

Page 169: ...03007F00 IRQ Stack SVC Stack USR Stack 4 WORDS 03007FE0 03007FA0 R 2 SP_svc 13 Complete processing with each system call SP_usr SP_irq 03007FA0 03007F00 03007F00 IRQ Stack SVC Stack USR Stack 4 WORDS 03007FE0 03007FA0 SP_svc 14 Return value to registers R0 R1 and R3 in cases where a system call provides a return value and then return to the user program SP_usr SP_irq 03007F00 IRQ Stack SVC Stack U...

Page 170: ...ata 8000004h 800009Fh 96h Device Type Complement Check Start Address Store the 32 bit ARM command B User program start address Nintendo Logo Character Data The Nintendo logo character data which is displayed when the game is started is stored here The Monitor ROM checks this data at start up therefore always store the data provided by Nintendo Game Title Store the Game title in this area Game Code...

Page 171: ...ation System custom 1Mbit flash Memory with security and patch functions in a Game Pak set the most significant bit to 1 Otherwise it is reset Other bits are system allocated area Mask ROM Version No Store the ROM version number here Complement Check The 2 s complement of the total of the data stored in address 80000A0h 80000BCh plus 19h is stored in this location Reserved Area This is a system al...

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