35
NED
XCM2080SAT4
/
XCM2040SAT4
UME-0006-04
4.3 Internal Circuit Configuration Block
The internal circuit configuration block of XCM2080SAT4
、
XCM2040SAT4 is shown
below.
FPGA receives the digital output from CMOS image sensor, and converts the data
into Camera Link Medium Configuration or Base Configuration.
Figure 4-3-1 Internal Circuit Configuration Block of Camera
Sequencer
Clock,
External trigger
CLISBee CMOS Image Sensor
Flash Memory
+12~15V
FPGA
Channel
Link
Driver 1
Indicator
(green LED)
X0±,X1±,
X2±,X3±,
XClk±
CC1±
CC2±
CC3±
CC4±
SerTFG±
LVDS
Receiver
LVDS
Driver・
Receiver
SerTC±
LVAL,FVAL
DVAL,CK
SP
PortA~C
Channel
Link
Driver 2
Y0±,Y1±,
Y2±,Y3±,
YClk±
LVAL,FVAL
DVAL,CK
SP
PortD~F
Round shape
connector
HR10A
SPI(settings)
DC Voltage
PD
512pixels
CDS
PGA
A
D
C
A
D
C
MUX
CDS
PGA
SPI
PD
512pixels
CDS
PGA
A
D
C
A
D
C
MUX
CDS
PGA
SPI
PD
512pixels
CDS
PGA
A
D
C
A
D
C
MUX
CDS
PGA
SPI
PD
512pixels
CDS
PGA
A
D
C
A
D
C
MUX
CDS
PGA
SPI