µ
PD75P3116
27
Data Sheet U11369EJ3V0DS
Instruction
Mnemonic
Operand
No. of Machine
Operation
Addressing
Skip
Group
Bytes
Cycle
Area
Condition
Subroutine
PUSH
rp
1
1
(SP–1)(SP–2)
←
rp, SP
←
SP–2
stack control
BS
2
2
(SP–1)
←
MBS, (SP–2)
←
RBS,
SP
←
SP–2
POP
rp
1
1
rp
←
(SP+1)(SP), SP
←
SP+2
BS
2
2
MBS
←
(SP+1), RBS
←
(SP), SP
←
SP+2
Interrupt
EI
2
2
IME(IPS.3)
←
1
control
IE
×××
2
2
IE
×××
←
1
DI
2
2
IME(IPS.3)
←
0
IE
×××
2
2
IE
×××
←
0
I/O
IN
Note 1
A, PORTn
2
2
A
←
PORTn (n=0 to 3, 5, 6, 8, 9)
XA, PORTn
2
2
XA
←
PORTn+
1
, PORTn (n=8)
OUT
Note 1
PORTn, A
2
2
PORTn
←
A (n=2 to 3, 5, 6, 8, 9)
PORTn, XA
2
2
PORTn+
1
, PORTn
←
XA (n=8)
CPU control
HALT
2
2
Set HALT Mode(PCC.2
←
1)
STOP
2
2
Set STOP Mode(PCC.3
←
1)
NOP
1
1
No Operation
Special
SEL
RBn
2
2
RBS
←
n (n=0 to 3)
MBn
2
2
MBS
←
n (n=0, 1, 15)
GETI
Notes 2, 3
taddr
1
3
• When using TBR instruction
*10
PC
13-0
←
(taddr)
5-0
+(taddr+1)
• When using TCALL instruction
(SP–4)(SP–1)(SP–2)
←
PC
11-0
(SP–3)
←
MBE, RBE, PC
13, 12
PC
13-0
←
(taddr)
5-0
+(taddr+1)
SP
←
SP–4
• When using instruction other than
Determined by
TBR or TCALL
referenced
Execute (taddr)(taddr+1) instructions
instruction
1
3
• When using TBR instruction
*10
PC
13-0
←
(taddr)
5-0
+(taddr+1)
4
• When using TCALL instruction
(SP–6)(SP–3)(SP–4)
←
PC
11-0
(SP–5)
←
0, 0, PC
13, 12
(SP–2)
←
X, X, MBE, RBE
PC
13-0
←
(taddr)
5-0
+(taddr+1)
SP
←
SP–6
3
• When using instruction other than
Determined by
TBR or TCALL
referenced
Execute (taddr)(taddr+1) instructions
instruction
Notes 1. Setting MBE = 0 or MBE = 1, MBS = 15 is required during the execution of the IN or OUT instruction.
2. The TBR and TCALL instructions are assembler quasi-directives for the GETI instruction table definitions.
3. The sections in double boxes are only supported in the Mk II mode. The other sections are only supported in
the Mk I mode.
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