NEC uPD75P3116 Datasheet Download

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PD75P3116

Data Sheet U11369EJ3V0DS

Instruction

Mnemonic

Operand

No. of Machine

Operation

Addressing

Skip

Group

Bytes

Cycle

Area

Condition

Subroutine

CALLA

Note

!addr1

(SP–6)(SP–3)(SP–4)

←

11-0

*11

stack control

(SP–5)

←

0, 0, PC

(SP–2)

←

X, X, MBE, RBE

13-0

←

addr1, SP

←

SP–6

CALL

Note

!addr

(SP–4)(SP–1)(SP–2)

←

11-0

(SP–3)

←

MBE, RBE, PC

13, 12

13-0

←

addr, SP

←

SP–4

(SP–6)(SP–3)(SP–4)

←

11-0

(SP–5)

←

0, 0, PC

13, 12

(SP–2)

←

X, X, MBE, RBE

13-0

←

addr, SP

←

SP–6

CALLF

Note

!faddr

(SP–4)(SP–1)(SP–2)

←

11-0

(SP–3)

←

MBE, RBE, PC

13, 12

13-0

←

000+faddr, SP

←

SP–4

(SP–6)(SP–3)(SP–4)

←

11-0

(SP–5)

←

0, 0, PC

13, 12

(SP–2)

←

X, X, MBE, RBE

13-0

←

000+faddr, SP

←

SP–6

RET

Note

MBE, RBE, PC

13, 12

←

(SP+1)

11-0

←

(SP)(SP+3)(SP+2)

←

SP+4

X, X, MBE, RBE

←

(SP+4)

11-0

←

(SP)(SP+3)(SP+2)

0, 0, PC

13, 12

←

(SP+1)

←

SP+6

RETS

Note

3+S

MBE, RBE, PC

13, 12

←

(SP+1)

Unconditional

11-0

←

(SP)(SP+3)(SP+2)

←

SP+4

then skip unconditionally

X, X, MBE, RBE

←

(SP+4)

11-0

←

(SP)(SP+3)(SP+2)

0, 0, PC

13, 12

←

(SP+1)

←

SP+6

then skip unconditionally

RETI

Note

MBE, RBE, PC

13, 12

←

(SP+1)

11-0

←

(SP)(SP+3)(SP+2)

PSW

←

(SP+4)(SP+5)

←

SP+6

0, 0, PC

13, 12

←

(SP+1)

11-0

←

(SP)(SP+3)(SP+2)

PSW

←

(SP+4)(SP+5), SP

←

SP+6

Note

The sections in double boxes are only supported in the Mk II mode. The other sections are only supported in the Mk I mode.

Summary of Contents for uPD75P3116

Page 1: ...ntrollers are microcontrollers with on chip one time PROM that are totally supported by NEC This support includes writing application programs marking screening and verification ORDERING INFORMATION P...

Page 2: ...2 duty 1 2 bias 1 3 duty 1 2 bias 1 3 duty 1 3 bias 1 4 duty 1 3 bias Timers 5 channels 8 bit timer event counter 3 channels Can be used as 16 bit timer event counter carrier generator and timer with...

Page 3: ...ENCES BETWEEN PD75P3116 AND PD753104 753106 753108 16 6 MEMORY CONFIGURATION 17 7 INSTRUCTION SET 19 8 ONE TIME PROM PROGRAM MEMORY WRITE AND VERIFY 28 8 1 Operation Modes for Program Memory Write Ver...

Page 4: ...83 S20 39 P82 S21 38 P81 S22 37 P80 S23 36 P23 BUZ 35 P22 PCL PTO2 34 P21 PTO1 33 P20 PTO0 64 COM3 63 COM2 62 COM1 61 COM0 60 S0 59 S1 58 S2 57 S3 56 S4 55 S5 54 S6 53 S7 52 S8 51 S9 50 S10 49 S11 1 B...

Page 5: ...0 to P83 Port 8 PTO0 to PTO2 Programmable timer output 0 to 2 P90 to P93 Port 9 BUZ Buzzer clock KR0 to KR3 Key return 0 to 3 PCL Programmable clock SCK Serial clock INT0 1 4 External vectored interru...

Page 6: ...P53 D7 P60 D0 to P63 D3 P80 to P83 Port 0 Port 1 Port 2 Port 3 Port 5 Port 6 Port 8 Port 9 P90 to P93 LCD controller driver 4 S16 P93 to S19 P90 4 S20 P83 to S23 P80 VLC0 VLC1 VLC2 SYNC P31 LCDCL P30...

Page 7: ...P20 I O PTO0 4 bit I O port Port 2 Input E B Connection of an internal pull up resistor can be P21 PTO1 specified by a software setting in 4 bit units P22 PCL PTO2 P23 BUZ P30 I O LCDCL MD0 Programma...

Page 8: ...P62 KR2 D2 P63 KR3 D3 P80 I O S23 4 bit I O port Port 8 Input H Connection of an internal pull up resistor can be P81 S22 specified by a software setting in 4 bit unitsNote 2 P82 S21 P83 S20 P90 I O...

Page 9: ...le input Asynchronous KR0 to KR3 I O P60 to P63 Parallel falling edge detection testable input Input F A X1 Input Ceramic crystal resonator connection for main system clock oscillation If using an ext...

Page 10: ...iving LCD BIAS Output Output for external split resistor cut Note 2 LCDCLNote 3 Output P30 MD0 Clock output for driving external expansion driver Input E B SYNCNote 3 Output P31 MD1 Clock output for s...

Page 11: ...P U R Type D Output disable P U R Pull Up Resistor Type A VDD P ch P U R enable P U R P U R Pull Up Resistor IN VDD P ch IN OUT P U R enable Data P U R Type D Output disable P U R Pull Up Resistor Typ...

Page 12: ...Data P U R Output disable P U R Pull Up Resistor N ch Pull up resistor that operates only when an input instruction is executed The current flows from VDD to a pin when the pin is at low level Note OU...

Page 13: ...n P22 PTO2 PCL P23 BUZ P30 LCDCL MD0 P31 SYNC MD1 P32 MD2 P33 MD3 P50 D4 to P53 D7 Input Connect to Vss Output Connect to Vss P60 KR0 D0 to P63 KR3 D3 Input Independently connect to Vss or VDD via a r...

Page 14: ...ks 0 and 1 No of stack bytes 2 bytes 3 bytes Instruction BRA addr1 instruction Not available Available CALLA addr1 instruction Instruction CALL addr instruction 3 machine cycles 4 machine cycles execu...

Page 15: ...BNote at the beginning of the program When using the Mk II mode be sure to initialize it to 000 BNote Note Set the desired value for Figure 4 1 Format of Stack Bank Selection Register Caution SBS3 is...

Page 16: ...16384 Data memory 4 bits 512 Mask options Pull up resistor for Available Not available Port 5 On chip not on chip can be specified Not on chip Split resistor for LCD driving power supply Wait time aft...

Page 17: ...r 6 bits INT1 start address lower 8 bits INTCSI start address higher 6 bits INTCSI start address lower 8 bits INTT0 start address higher 6 bits INTT0 start address lower 8 bits INTT1 INTT2 start addre...

Page 18: ...selected as the stack area 32 4 256 4 224 4 128 4 0 1 15 000H 01FH 020H 0FFH 100H 1E0H 1DFH 1F7H 1F8H F80H FFFH General purpose register area Display data memory Data area static RAM 512 4 Stack area...

Page 19: ...can be entered for fmem and pmem are restricted Representation Coding Format reg X A B C D E H L reg1 X B C D E H L rp XA BC DE HL rp1 BC DE HL rp2 BC DE rp XA BC DE HL XA BC DE HL rp 1 BC DE HL XA B...

Page 20: ...ister pair BC DE Expansion register pair DE HL Expansion register pair HL PC Program counter SP Stack pointer CY Carry flag bit accumulator PSW Program status word MBE Memory bank enable flag RBE Regi...

Page 21: ...te 3 byte instructions BR addr BRA addr1 CALL addr and CALLA addr1 Caution The GETI instruction is skipped for one machine cycle One machine cycle equals one cycle tCY of the CPU clock Use the PCC set...

Page 22: ...XA HL 2 2 XA HL 1 HL A 1 1 HL A 1 HL XA 2 2 HL XA 1 A mem 2 2 A mem 3 XA mem 2 2 XA mem 3 mem A 2 2 mem A 3 mem XA 2 2 mem XA 3 A reg 2 2 A reg XA rp 2 2 XA rp reg1 A 2 2 reg1 A rp 1 XA 2 2 rp 1 XA XC...

Page 23: ...XA rp 2 2 XA CY XA rp CY rp 1 XA 2 2 rp 1 CY rp 1 XA CY SUBS A HL 1 1 S A A HL 1 borrow XA rp 2 2 S XA XA rp borrow rp 1 XA 2 2 S rp 1 rp 1 XA borrow SUBC A HL 1 1 A CY A HL CY 1 XA rp 2 2 XA CY XA rp...

Page 24: ...ip if mem bit 1 3 mem bit 1 fmem bit 2 2 S Skip if fmem bit 1 4 fmem bit 1 pmem L 2 2 S Skip if pmem7 2 L3 2 bit L1 0 1 5 pmem L 1 H mem bit 2 2 S Skip if H mem3 0 bit 1 1 H mem bit 1 SKF mem bit 2 2...

Page 25: ...t the most appropriate instruction among the following BRA addr1 BR addr BRCB caddr BR addr1 addr 3 3 PC13 0 addr 6 addr 1 2 PC13 0 addr 7 addr1 1 2 PC13 0 addr1 PCDE 2 3 PC13 0 PC13 8 DE PCXA 2 3 PC1...

Page 26: ...12 PC13 0 000 faddr SP SP 4 3 SP 6 SP 3 SP 4 PC11 0 SP 5 0 0 PC13 12 SP 2 X X MBE RBE PC13 0 000 faddr SP SP 6 RETNote 1 3 MBE RBE PC13 12 SP 1 PC11 0 SP SP 3 SP 2 SP SP 4 X X MBE RBE SP 4 PC11 0 SP...

Page 27: ...3 When using TBR instruction 10 PC13 0 taddr 5 0 taddr 1 When using TCALL instruction SP 4 SP 1 SP 2 PC11 0 SP 3 MBE RBE PC13 12 PC13 0 taddr 5 0 taddr 1 SP SP 4 When using instruction other than Det...

Page 28: ...Operation mode selection pin for program memory write verify D0 P60 to D3 P63 8 bit data I O pins for program memory write verify lower 4 bits D4 P50 to D7 P53 higher 4 bits VDD Pin where power suppl...

Page 29: ...mode If the data is written go to 8 and if not repeat 6 and 7 8 Additional write X Number of write operations from 6 and 7 1 ms 9 Apply four pulses to the X1 pin to increment the program memory addres...

Page 30: ...n unused pins to VSS via resistors Set the X1 pin to low 2 Supply 5 V to the VDD and VPP pins 3 Wait 10 s 4 Select the program memory address zero clear mode 5 Supply 6 V to VDD and 12 5 V to VPP 6 Se...

Page 31: ...r the required data is written and the PROM is stored under the temperature and time conditions shown below the PROM should be verified via screening Storage Temperature Storage Time 125 C 24 hours NE...

Page 32: ...ambient TA 40 to 85Note C temperature Storage temperature Tstg 65 to 150 C Note When LCD is driven in normal mode TA 10 to 85 C Caution Product quality may suffer if the absolute maximum rating is ex...

Page 33: ...V VDD 2 7 V and the oscillation frequency is 4 19 MHz fx 6 0 MHz setting the processor clock control register PCC to 0011 makes 1 machine cycle less than the required 0 95 s Therefore set PCC to a val...

Page 34: ...e subsystem clock oscillator wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance Keep the wiring length as short as possibl...

Page 35: ...s 2 3 6 8 and 9 IOH 1 0 mA VDD 0 5 V Output voltage low VOL1 SCK SO Ports 2 3 5 6 8 and 9 IOL 15 mA 0 2 2 0 V VDD 4 5 to 5 5 V IOL 1 6 mA 0 4 V VOL2 SB0 SB1 When N ch open drain 0 2VDD V pull up resis...

Page 36: ...DD 3 0 V 10 5 5 18 A VDD 2 0 V 10 2 2 7 A VDD 3 0 V TA 25 C 5 5 12 A VDD 3 0 V 10 4 0 12 A VDD 3 0 V 4 0 8 A TA 25 C IDD5 XT1 0 VNote 10 VDD 5 0 V 10 0 05 10 A STOP mode VDD 3 0 V TA 40 to 85 C 0 02 5...

Page 37: ...s Interrupt input high tINTH tINTL INT0 IM02 0 Note 2 s low level width IM02 1 10 s INT1 2 4 10 s KR0 to KR7 10 s RESET low level width tRSL 10 s Notes 1 Thecycletime minimuminstruction execution tim...

Page 38: ...mode read this parameter as SB0 or SB1 instead 2 RL and CL are the load resistance and load capacitance of the SO output lines respectively 2 wire and 3 wire serial I O mode SCK External clock input...

Page 39: ...el width tSBH tKCY3 ns Note RL and CL are the load resistance and load capacitance of the SB0 and SB1 output lines respectively SBI mode SCK External clock input slave TA 40 to 85 C VDD 1 8 to 5 5 V P...

Page 40: ...ming Test Points Excluding X1 XT1 Input Clock Timing TI0 TI1 TI2 Timing TI0 TI1 TI2 1 fTI tTIL tTIH X1 input 1 fX tXL tXH 0 1 V VDD 0 1 V XT1 input 1 fXT tXTL tXTH 0 1 V VDD 0 1 V VIH MIN VIL MAX VIH...

Page 41: ...eet U11369EJ3V0DS Serial Transfer Timing 3 wire serial I O mode 2 wire serial I O mode tKCY1 2 tKL1 2 tKH1 2 SCK SI SO tSIK1 2 tKSI1 2 tKSO1 2 Input data Output data tKSO1 2 tSIK1 2 tKL1 2 tKH1 2 SCK...

Page 42: ...tKSO3 4 SCK SB0 1 tKL3 4 tSBK tKSB tKCY3 4 tKH3 4 tKSI3 4 tSIK3 4 tKSO3 4 SCK SB0 1 tKL3 4 tSBK tSBH tSBL tKSB Serial Transfer Timing Bus release signal transfer Command signal transfer Interrupt inpu...

Page 43: ...est Note 2 ms Notes 1 The oscillation stabilization wait time is the time during which the CPU operation is stopped to prevent unstable operation at the start of oscillation 2 Depends on the basic int...

Page 44: ...elease Signal STOP Mode Release by Interrupt Signal VDD RESET STOP instruction execution STOP mode Data retention mode Internal reset operation HALT mode Operating mode tSREL tWAIT tSREL tWAIT VDD STO...

Page 45: ...from MD0 tAH 2 s Data hold time from MD0 tDH 2 s Data output float delay time from MD0 tDF 0 130 ns VPP setup time to MD3 tVPS 2 s VDD setup time to MD3 tVDS 2 s Initial program pulse width tPW 0 95...

Page 46: ...1R tM0S tOPW tM1S tM1H tPCR tM3S tM3H Data input Data output Data input Data input VPP VDD VDD 1 VDD VPP VDD X1 D0 P60 to D3 P60 D4 P50 to D7 P53 MD0 P30 MD1 P31 MD2 P32 MD3 P33 tVPS tVDS VPP VDD VDD...

Page 47: ...clock HALT mode 32 kHz oscillation XT1 XT2 X1 X2 Crystal resonator 6 0 MHz Crystalresonator 32 768 kHz 330 k 22 pF 22 pF 22 pF 22 pF VDD VDD Main system clock STOP mode 32 kHz oscillation SOS 1 1 and...

Page 48: ...e VDD V Supply current I DD mA VDD VDD PCC 0010 Main system clock HALT mode 32 kHz oscillation Subsystem clock HALT mode SOS 1 0 and main system clock STOP mode 32 kHz oscillation SOS 1 0 Subsystem cl...

Page 49: ...of its true position T P at maximum material condition ITEM MILLIMETERS A B D G 17 6 0 4 14 0 0 2 0 8 T P 1 0 J 17 6 0 4 K P64GC 80 AB8 5 C 14 0 0 2 I 0 15 1 8 0 2 L 0 8 0 2 F 1 0 N P Q 0 10 2 55 0 1...

Page 50: ...osition T P at maximum material condition ITEM MILLIMETERS A B D G 14 8 0 4 12 0 0 2 0 13 1 125 I 14 8 0 4 J C 12 0 0 2 H 0 32 0 08 0 65 T P K 1 4 0 2 L 0 6 0 2 F 1 125 P64GK 65 8A8 3 N P Q 0 10 1 4 0...

Page 51: ...P at maximum material condition ITEM MILLIMETERS A B D G 17 2 0 2 14 0 0 2 0 8 T P 1 0 J 17 2 0 2 K C 14 0 0 2 I 0 20 1 6 0 2 L 0 8 F 1 0 N P Q 0 10 1 4 0 1 0 127 0 075 U 0 886 0 15 R S 3 1 7 MAX T 0...

Page 52: ...ax package surface temperature Partial heating Pin temperature 300 C max Time 3 seconds max per pin row Caution Do not use different soldering methods together except for partial heating 2 PD75P3116GK...

Page 53: ...nds max at 210 C or higher IR35 00 2 Count Twice or less VPS Package peak temperature 215 C Time 40 seconds max at 200 C or higher VP15 00 2 Count Twice or less Wave soldering Solder bath temperature...

Page 54: ...le When Mk I mode Unavailable CALLA addr1 When Mk II mode Available MOVT XA BCDE Available MOVT XA BCXA BR BCDE BR BCXA CALL addr 3 machine cycles Mk I mode 3 machine cycles Mk II mode 4 machine cycle...

Page 55: ...available 3 wire serial I O mode MSB LSB can be selected for transfer first bit 2 wire serial I O mode SBI mode SOS register Feedback resistor None Contained cut flag SOS 0 Sub oscillator current None...

Page 56: ...9800 Series MS DOSTM 3 5 2HD S5A13RA75X Ver 3 30 to Ver 6 2Note IBM PC AT Refer to OS for 3 5 2HC S7B13RA75X or compatibles IBM PCs Device file Host Machine Part Number OS Supply Medium Product Name P...

Page 57: ...PD75P3116GK 8A8 It can be used when connected to the PG 1500 PA 75P3116GC 8BS This is a PROM programmer adapter for the PD75P3116GC 8BS It can be used when connected to the PG 1500 Software PG 1500 co...

Page 58: ...n conversion socket EV 9200GC 64 to facilitate connection with the target system EP 753108GK R This is an emulation probe for the PD75P3116GK When being used it is connected with the IE 75001 R and th...

Page 59: ...M PCs are supported OS Version PC DOSTM Ver 3 1 to 6 3 J6 1 VNote to J6 3 VNote MS DOS Ver 5 0 to 6 2 5 0 VNote to 6 2 VNote IBM DOSTM J5 02 VNote Note Only English mode is supported Caution Ver 5 0 a...

Page 60: ...1 E EV 9200GC 64 B D C M N L K R Q I H P O S T J G No 1 pin index EV 9200GC 64 G0E ITEM MILLIMETERS INCHES A B C D E F G H I J K L M N O P Q R S T 18 8 14 1 14 1 18 8 4 C 3 0 0 8 6 0 15 8 18 5 6 0 15...

Page 61: ...02 2 36 0 03 2 2 0 1 1 57 0 03 0 768 0 583 0 583 0 768 0 236 0 236 0 197 0 093 0 087 0 062 0 8 0 02 15 12 0 0 05 0 8 0 02 15 12 0 0 05 0 002 0 001 0 003 0 002 0 002 0 001 0 003 0 002 0 004 0 003 0 004...

Page 62: ...ES B 0 65x15 9 75 0 026x0 591 0 384 C 0 65 0 026 A 18 4 0 724 D H 0 65x15 9 75 0 026x0 591 0 384 I 11 85 0 467 J 18 4 0 724 E 10 15 0 400 F 12 55 0 494 K C 2 0 C 0 079 L 12 45 0 490 M Q 11 1 0 437 R 1...

Page 63: ...nversion Socket Distance Between In Circuit Emulator Conversion Adapter and Conversion Socket or Conversion Adapter EP 753108GC R EV 9200GC 64 700 mm EP 753108GK R TGK 064SBW 700 mm Figure B 4 Distanc...

Page 64: ...ircuit emulator IE 75001 R External sense clips Target system Conversion socket EV 9200GC 64 64 pin GC EP 753108GC R Ground clip 35 mm 35 mm 18 5 mm 18 5 mm 8 mm Target system Conversion adapter TGK 0...

Page 65: ...ument No RA75X Assembler Package Operation U12622E Language U12385E Structured Assembler Preprocessor U12598E Documents Related to Development Tools Hardware User s Manuals Document Name Document No I...

Page 66: ...chnology Manual C10535E Quality Grades on NEC Semiconductor Devices C11531E NEC Semiconductor Device Reliability Quality Control System C10983E Guide to Prevent Damage for Semiconductor Devices by Ele...

Page 67: ...PD75P3116 67 Data Sheet U11369EJ3V0DS MEMO...

Page 68: ...e No connection for CMOS device inputs can be cause of malfunction If no connection is provided to the input pins it is possible that an internal input level may be generated due to noise etc hence ca...

Page 69: ...ong Ltd Hong Kong Tel 2886 9318 Fax 2886 9022 9044 NEC Electronics Hong Kong Ltd Seoul Branch Seoul Korea Tel 02 528 0303 Fax 02 528 4411 NEC Electronics Shanghai Ltd Shanghai P R China Tel 021 6841 1...

Page 70: ...onsibility for any losses incurred by customers or third parties arising from the use of these circuits software and information While NEC endeavours to enhance the quality reliability and safety of N...

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