NEC U789436 Series User Manual Download Page 183

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CHAPTER 9 WATCHDOG TIMER

User’s Manual U15075EJ2V1UD

183

9.2 Watchdog Timer Configuration

The watchdog timer includes the following hardware.

Table 9-3. Configuration of Watchdog Timer

Item Configuration

Control registers

Watchdog timer clock select register (WDCS)

Watchdog timer mode register (WDTM)

Figure 9-1. Block Diagram of Watchdog Timer

Internal bus

Prescaler

Selector

Controller

7-bit counter

WDTIF

WDTMK

TCL22 TCL21 TCL20

Watchdog timer clock select register

(WDCS)

Watchdog timer mode register (WDTM)

Clear

WDTM4

RUN

WDTM3

INTWDT
Maskable
interrupt request

RESET

INTWDT
Non-maskable
interrupt request

Summary of Contents for U789436 Series

Page 1: ...426 µPD789446 µPD789435 µPD789455 µPD789436 µPD789456 µPD78F9436 µPD78F9456 µPD789426 789436 789446 789456 Subseries 8 Bit Single Chip Microcontrollers Printed in Japan Document No U15075EJ2V1UD00 2nd edition Date Published August 2005 N CP K ...

Page 2: ...2 User s Manual U15075EJ2V1UD MEMO ...

Page 3: ... including work benches and floors should be grounded The operator should be grounded using a wrist strap Semiconductor devices must not be touched with bare hands Similar precautions need to be taken for PW boards with mounted semiconductor devices STATUS BEFORE INITIALIZATION Power on does not necessarily define the initial status of a MOS device Immediately after the power source is turned ON d...

Page 4: ...demarks or trademarks of Microsoft Corporation in the United States and or other countries PC AT is a trademark of International Business Machines Corporation HP9000 series 700 and HP UX are trademarks of Hewlett Packard Company SPARCstation is a trademark of SPARC International Inc Solaris and SunOS are trademarks of Sun Microsystems Inc ...

Page 5: ...fety of NEC Electronics products customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely To minimize risks of damage to property or injury including death to persons arising from defects in NEC Electronics products customers must incorporate sufficient safety measures in their design such as redundancy fire containment and anti failure features NEC Ele...

Page 6: ...anch Seoul Korea Tel 02 558 3737 NEC Electronics Shanghai Ltd Shanghai P R China Tel 021 5888 5400 NEC Electronics Taiwan Ltd Taipei Taiwan Tel 02 2719 2377 NEC Electronics Singapore Pte Ltd Novena Square Singapore Tel 6253 8311 J05 6 NEC Electronics Europe GmbH Duesseldorf Germany Tel 0211 65030 Sucursal en España Madrid Spain Tel 091 504 27 87 Vélizy Villacoublay France Tel 01 30 67 58 00 Succur...

Page 7: ...User s Manual U15075EJ2V1UD 7 MEMO ...

Page 8: ...ion Instruction set Instruction description How to Use This Manual It is assumed that the readers of this manual have general knowledge of electrical engineering logic circuits and microcontrollers To understand the overall functions of the µPD789426 789436 789446 and 789456 Subseries Read this manual in the order of the CONTENTS How to read register formats The name of a bit whose number is enclo...

Page 9: ... User s Manual U11047E Documents Related to Development Software Tools User s Manuals Document Name Document No Operation U14876E Language U14877E RA78K0S Assembler Package Structured Assembly Language U11623E Operation U14871E CC78K0S C Compiler Language U14872E Operation Windows TM Based U15373E SM78K Series System Simulator Ver 2 30 or Later External Part User Open Interface Specification U1580...

Page 10: ...ages X13769X Semiconductor Device Mount Manual Note Quality Grades on NEC Semiconductor Devices C11531E NEC Semiconductor Device Reliability Quality Control System C10983E Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge ESD C11892E Note See the Semiconductor Device Mount Manual website http www necel com pkg en mount index html Caution The related documents listed abov...

Page 11: ...N FUNCTIONS 37 2 1 List of Pin Functions 37 2 2 Description of Pin Functions 40 2 2 1 P00 to P03 Port 0 40 2 2 2 P10 P11 Port 1 40 2 2 3 P20 to P26 Port 2 40 2 2 4 P30 to P33 Port 3 41 2 2 5 P50 to P53 Port 5 41 2 2 6 P60 to P65 Port 6 41 2 2 7 P70 to P72 Port 7 42 2 2 8 P80 P81 Port 8 42 2 2 9 P90 to P97 Port 9 42 2 2 10 S0 to S14 42 2 2 11 COM0 to COM3 42 2 2 12 VLC0 to VLC2 42 2 2 13 CAPH CAPL ...

Page 12: ...ddressing 70 3 4 1 Direct addressing 70 3 4 2 Short direct addressing 71 3 4 3 Special function register SFR addressing 72 3 4 4 Register addressing 73 3 4 5 Register indirect addressing 74 3 4 6 Based addressing 75 3 4 7 Stack addressing 75 CHAPTER 4 PORT FUNCTIONS 76 4 1 Port Functions 76 4 2 Port Configuration 79 4 2 1 Port 0 80 4 2 2 Port 1 81 4 2 3 Port 2 82 4 2 4 Port 3 88 4 2 5 Port 5 90 4 ...

Page 13: ...6 Bit Timer 90 123 6 4 16 Bit Timer 90 Operation 127 6 4 1 Operation as timer interrupt 127 6 4 2 Operation as timer output 129 6 4 3 Capture operation 130 6 4 4 16 bit timer counter 90 readout 131 6 4 5 Buzzer output operation 132 6 5 Notes on 16 Bit Timer 90 133 6 5 1 Notes on using 16 bit timer 90 133 6 5 2 Restrictions on rewriting 16 bit compare register 90 135 CHAPTER 7 8 BIT TIMERS 50 60 13...

Page 14: ...o 8 Bit A D Converter 197 CHAPTER 11 10 BIT A D CONVERTER µPD789436 AND 789456 SUBSERIES 201 11 1 10 Bit A D Converter Functions 201 11 2 10 Bit A D Converter Configuration 201 11 3 10 Bit A D Converter Control Registers 204 11 4 10 Bit A D Converter Operation 206 11 4 1 Basic operation of 10 bit A D converter 206 11 4 2 Input voltage and conversion result 207 11 4 3 Operation mode of 10 bit A D c...

Page 15: ... operation 278 14 4 3 Multiple interrupt servicing 279 14 4 4 Putting interrupt requests on hold 281 CHAPTER 15 STANDBY FUNCTION 282 15 1 Standby Function and Configuration 282 15 1 1 Standby function 282 15 1 2 Register controlling standby function 283 15 2 Standby Function Operation 284 15 2 1 HALT mode 284 15 2 2 STOP mode 287 CHAPTER 16 RESET FUNCTION 290 CHAPTER 17 µPD78F9436 78F9456 294 17 1...

Page 16: ...ING CONDITIONS 337 APPENDIX A DEVELOPMENT TOOLS 340 A 1 Software Package 342 A 2 Language Processing Software 342 A 3 Control Software 343 A 4 Flash Memory Writing Tools 343 A 5 Debugging Tools Hardware 344 A 6 Debugging Tools Software 345 APPENDIX B NOTES ON TARGET SYSTEM DESIGN 346 APPENDIX C REGISTER INDEX 350 C 1 Register Index Alphabetic Order of Register Name 350 C 2 Register Index Alphabeti...

Page 17: ...rogram Status Word Configuration 60 3 15 Stack Pointer Configuration 62 3 16 Data to Be Saved to Stack Memory 62 3 17 Data to Be Restored from Stack Memory 62 3 18 General Purpose Register Configuration 63 4 1 Port Types µPD789426 789436 Subseries 76 4 2 Port Types µPD789446 789456 Subseries 77 4 3 Block Diagram of P00 to P03 80 4 4 Block Diagram of P10 and P11 81 4 5 Block Diagram of P20 82 4 6 B...

Page 18: ...d CPU Clock Crystal Ceramic Oscillation 117 5 11 Switching Between System Clock and CPU Clock RC Oscillation 118 6 1 Block Diagram of 16 Bit Timer 90 121 6 2 Format of 16 Bit Timer Mode Control Register 90 124 6 3 Format of Buzzer Output Control Register 90 125 6 4 Format of Port Mode Registers 2 3 126 6 5 Settings of 16 Bit Timer Mode Control Register 90 for Timer Interrupt Operation 127 6 6 Timi...

Page 19: ...rator Operation When CR60 N CRH60 M M N 168 7 21 Timing of Carrier Generator Operation When CR60 CRH60 N 169 7 22 Operation Timing in PWM Free Running Mode When Rising Edge Is Selected 171 7 23 Operation Timing When Overwriting CR50 When Rising Edge Is Selected 171 7 24 Operation Timing in PWM Free Running Mode When Both Edges Are Selected 172 7 25 Operation Timing in PWM Free Running Mode When Bo...

Page 20: ... 211 11 10 Analog Input Pin Treatment 212 11 11 A D Conversion End Interrupt Request Generation Timing 213 11 12 AVDD Pin Handling 213 12 1 Block Diagram of Serial Interface 20 215 12 2 Block Diagram of Baud Rate Generator 20 216 12 3 Format of Serial Operation Mode Register 20 218 12 4 Format of Asynchronous Serial Interface Mode Register 20 219 12 5 Format of Asynchronous Serial Interface Status...

Page 21: ...Program Status Word 274 14 7 Format of Key Return Mode Register 00 275 14 8 Block Diagram of Falling Edge Detector 275 14 9 Flow from Generation of Non Maskable Interrupt Request to Acknowledgment 277 14 10 Timing of Non Maskable Interrupt Request Acknowledgment 277 14 11 Non Maskable Interrupt Request Acknowledgment 277 14 12 Interrupt Request Acknowledgment Program Algorithm 278 14 13 Interrupt ...

Page 22: ...ring Example for Flash Writing Adapter Using 3 Wire Serial I O 302 17 9 Wiring Example for Flash Writing Adapter Using UART 303 A 1 Development Tools 341 B 1 Distance Between In Circuit Emulator and Conversion Adapter When 64GB Is Used 346 B 2 Connection Conditions of Target System When NP 64GB TQ Is Used 347 B 3 Connection Conditions of Target System When NP H64GB TQ Is Used 347 B 4 Distance Betw...

Page 23: ...6 3 Settings of Capture Edge 130 6 4 Buzzer Frequency of 16 Bit Timer 90 132 7 1 Operation Modes 137 7 2 8 Bit Timer Configuration 138 7 3 Interval Time of Timer 50 151 7 4 Interval Time of Timer 60 151 7 5 Square Wave Output Range of Timer 50 During fX 5 0 MHz Operation 156 7 6 Square Wave Output Range of Timer 60 During fX 5 0 MHz Operation 157 7 7 Interval Time with 16 Bit Resolution During fX ...

Page 24: ...oller Driver 251 13 3 Frame Frequencies Hz 255 13 4 COM Signals 258 13 5 Select and Deselect Voltages COM0 to COM2 260 13 6 Select and Deselect Voltages COM0 to COM3 263 13 7 Output Voltages of VLC0 to VLC2 Pins 266 14 1 Interrupt Source List 268 14 2 Flags Corresponding to Interrupt Request Signal Name 270 14 3 Time from Generation of Maskable Interrupt Request to Servicing 278 15 1 HALT Mode Ope...

Page 25: ...lation Minimum instruction execution time can be changed from high speed 0 5 µs 4 0 MHz operation with main system clock to ultra low speed 122 µs 32 768 kHz operation with subsystem clock RC oscillation I O ports 40 µPD789426 789436 Subseries 30 µPD789446 789456 Subseries Timer 5 channels 16 bit timer 1 channel 8 bit timer 2 channels Watch timer 1 channel Watchdog timer 1 channel A D converter 8 ...

Page 26: ...lash memory µPD78F9456GB 8EU 64 pin plastic LQFP fine pitch 10 10 Flash memory µPD789425GK 9ET A 64 pin plastic TQFP fine pitch 12 12 Mask ROM µPD789426GK 9ET A 64 pin plastic TQFP fine pitch 12 12 Mask ROM µPD789435GK 9ET A 64 pin plastic TQFP fine pitch 12 12 Mask ROM µPD789436GK 9ET A 64 pin plastic TQFP fine pitch 12 12 Mask ROM µPD789445GK 9ET A 64 pin plastic TQFP fine pitch 12 12 Mask ROM µ...

Page 27: ...1 22 23 24 25 26 27 28 29 30 31 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P50 P51 P52 P53 IC VPP XT1 XT2 VDD VSS X1 CL1 X2 CL2 RESET P00 KR0 P01 KR1 P02 KR2 P03 KR3 32 CAPH CAPL V LC0 V LC1 V LC2 COM0 COM1 COM2 COM3 S0 S1 S2 S3 S4 P90 P91 P62 ANI2 P63 ANI3 P64 ANI4 P65 ANI5 AVDD P72 P71 P70 P81 P80 P97 P96 P95 P94 P93 P92 P20 P21 BZO90 P22 SS20...

Page 28: ... 26 27 28 29 30 31 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P50 P51 P52 P53 IC VPP XT1 XT2 VDD VSS X1 CL1 X2 CL2 RESET P00 KR0 P01 KR1 P02 KR2 P03 KR3 32 CAPH CAPL V LC0 V LC1 V LC2 COM0 COM1 COM2 COM3 S0 S1 S2 S3 S4 S5 S6 P62 ANI2 P63 ANI3 P64 ANI4 P65 ANI5 AVDD P72 P71 P70 S14 S13 S12 S11 S10 S9 S8 S7 P20 P21 BZO90 P22 SS20 P23 SCK20 ASCK20 ...

Page 29: ...K20 Serial clock COM0 to COM3 Common output SI20 Serial input CPT90 Capture trigger input SO20 Serial output IC Internally connected TMI60 Timer input INTP0 to INTP3 External interrupt input TO90 TO50 TO60 KR0 to KR3 Key return TO61 Timer output P00 to P03 Port 0 TxD20 Transmit data P10 P11 Port 1 VDD Power supply P20 to P26 Port 2 VLC0 to VLC2 LCD power supply P30 to P33 Port 3 VPP Programming po...

Page 30: ...A PD789134A PD789177 PD789167 30 pin 30 pin PD789104A PD789114A PD789167 with enhanced A D converter 10 bits PD789104A with enhanced timer PD789124A with enhanced A D converter 10 bits RC oscillation version of the PD789104A PD789104A with enhanced A D converter 10 bits PD789026 with added 8 bit A D converter and multiplier PD789104A with added EEPROM PD789146 with enhanced A D converter 10 bits P...

Page 31: ...24 KB 3 ch 1 ch 8 ch 31 µPD789156 4 ch µPD789146 8 KB to 16 KB 4 ch On chip EEPROM µPD789134A 4 ch µPD789124A 4 ch RC oscillation version µPD789114A 4 ch Small scale package general purpose applications and A D converter µPD789104A 2 KB to 8 KB 1 ch 1 ch 1 ch 4 ch 1 ch UART 1 ch 20 1 8 V µPD789835 24 KB to 60 KB 6 ch 3 ch 37 1 8 V Note µPD789830 24 KB 1 ch 1 ch UART 1 ch 30 2 7 V Dot LCD supported...

Page 32: ...8 ch 1 ch UART 1 ch 30 4 0 V µPD789852 24 KB to 32 KB 3 ch 8 ch 3 ch UART 2 ch 31 On chip bus controller µPD789850A 16 KB 1 ch 1 ch 1 ch 4 ch 2 ch UART 1 ch 18 4 0 V µPD789861 RC oscillation version on chip EEPROM µPD789860 4 KB 2 ch 14 Keyless entry µPD789862 16 KB 1 ch 2 ch 1 ch 1 ch UART 1 ch 22 1 8 V On chip EEPROM VFD drive µPD789871 4 KB to 8 KB 3 ch 1 ch 1 ch 1 ch 33 2 7 V Meter control µPD...

Page 33: ...t timer event counter TO60 P32 CPT90 P30 VLC0 to VLC2 CAPH CAPL LCD controller driver P50 to P53 Port 5 System control RESET X1 CL1 X2 CL2 XT1 XT2 Interrupt control INTP0 P30 INTP1 P31 INTP2 P32 INTP3 P33 KR0 P00 to KR3 P03 TO61 P33 BZO90 P21 Serial interface 20 SCK20 ASCK20 P23 SI20 RxD20 P25 SO20 TxD20 P24 SS20 P22 A D converter ANI0 P60 to ANI5 P65 AVSS AVDD P70 to P72 Port 7 P60 to P65 Port 6 ...

Page 34: ...ed 16 bit timer event counter TO60 P32 CPT90 P30 VLC0 to VLC2 CAPH CAPL LCD controller driver P50 to P53 Port 5 System control RESET X1 CL1 X2 CL2 XT1 XT2 Interrupt control TO61 P33 BZO90 P21 Serial interface 20 SCK20 ASCK20 P23 SI20 RxD20 P25 SO20 TxD20 P24 SS20 P22 A D converter ANI0 P60 to ANI5 P65 AVSS AVDD P70 to P72 Port 7 P60 to P65 Port 6 INTP0 P30 INTP1 P31 INTP2 P32 INTP3 P33 KR0 P00 to ...

Page 35: ...OS I O 30 CMOS input 6 N ch open drain 4 Total 30 CMOS I O 20 CMOS input 6 N ch open drain 4 Timers 16 bit timer 1 channel 8 bit timer 2 channels Watch timer 1 channel Watchdog timer 1 channel A D converter 8 bit resolution 6 channels µPD789426 789446 Subseries 10 bit resolution 6 channels µPD789436 789456 Subseries Serial interfaces Switchable between 3 wire serial I O mode and UART mode 1 channe...

Page 36: ... 2 Operation mode External event counter 1 channel Timer outputs 1 1 2 Square wave outputs 1 2 Capture 1 input Function Interrupt sources 1 1 1 2 2 Notes 1 The watch timer can perform both watch timer and interval timer functions at the same time 2 The watchdog timer has the watchdog timer and interval timer functions However use the watchdog timer by selecting either the watchdog timer function o...

Page 37: ...port Input output can be specified in 1 bit units When used as an input port an on chip pull up resistor can be specified by setting pull up resistor option register B2 PUB2 Input TO90 P30 INTP0 CPT90 P31 INTP1 TO50 TMI60 P32 INTP2 TO60 P33 I O Port 3 4 bit I O port Input output can be specified in 1 bit units When used as an input port an on chip pull up resistor can be specified by setting pull ...

Page 38: ... 1 bit units When used as an input port an on chip pull up resistor can be specified by setting pull up resistor option register B8 PUB8 Input P90 to P97 Note I O Port 9 8 bit I O port Input output can be specified in 1 bit units When used as an input port an on chip pull up resistor can be specified by setting pull up resistor option register B9 PUB9 Input Note µPD789426 789436 Subseries only ...

Page 39: ...t Input P30 INTP0 TO50 Output 8 bit timer TM50 output Input P31 INTP1 TMI40 TO60 Output Input P32 INTP2 TO61 Output 8 bit timer TM60 output Input P33 INTP33 TMI60 Input External count clock input to timer 40 Input P31 INTP1 TO50 ANI0 to ANI5 Input A D converter analog input Input P60 to P65 S0 to S4 Output Output S5 to S14 Note 1 Output LCD controller driver segment signal output Output COM0 to CO...

Page 40: ...cified by setting pull up resistor option register 0 PU0 in port units 2 2 3 P20 to P26 Port 2 These pins constitute a 7 bit I O port In addition these pins enable buzzer output timer output serial interface data I O and serial clock I O Port 2 can be specified in the following operation modes in 1 bit units 1 Port mode In this mode P20 to P26 function as a 7 bit I O port Port 2 can be set in the ...

Page 41: ...n register B3 PUB3 in 1 bit units 2 Control mode In this mode P30 to P33 function as timer I O and external interrupt input a TMI60 This is the external clock input pin to timer 60 b TO50 TO60 TO61 These are the timer output pins of timer 50 and timer 60 c CPT90 This is the capture edge input pin of 16 bit timer 90 d INTP0 to INTP3 These are external interrupt input pins for which valid edges risi...

Page 42: ...use of an on chip pull up resistor can be specified by setting pull up resistor option register B9 PUB9 in port units Note Only the µPD789426 and µPD789436 Subseries 2 2 10 S0 to S14Note These pins are segment signal output pins for the LCD controller driver Note S0 to S4 in the case of the µPD789426 and 789436 Subseries 2 2 11 COM0 to COM3 These pins are common signal output pins for the LCD cont...

Page 43: ...following ways Independently connect to a 10 kΩ pull down resistor By using a jumper on the board connect directly to the dedicated flash programmer in the programming mode or to VSS in the normal operation mode 2 2 21 IC mask ROM version only The IC Internally Connected pin is used to set the µPD789426 789436 789446 and 789456 Subseries in the test mode before shipment In the normal operation mod...

Page 44: ...Input Independently connect to VSS via a resistor Output Leave open P50 to P53 Mask ROM version 13 W P50 to P53 Flash memory version 13 V I O Input Connect directly to VSS Output Leave this pin open at low level output after clearing the output latch of the port to 0 P60 ANI0 to P65 ANI5 9 C Input Connect directly to VDD or VSS P70 to P72 P80 P81 Note 1 P90 to P97 Note 1 5 A I O Input Independentl...

Page 45: ...Output disable Input enable VDD P ch VDD P ch IN OUT N ch VSS VSS Output data Output disable IN OUT VDD N ch Middle voltage input buffer Input enable Pull up resistor mask option Type 8 A Type 17 Pull up enable Data Output disable VDD P ch VDD P ch IN OUT N ch VSS P ch P ch VLC0 VLC1 N ch P ch N ch VLC2 SEG data P ch OUT N ch N ch Type 9 C Type 18 IN Comparator VREF Threshold voltage AVSS P ch N c...

Page 46: ...s Figure 3 1 Memory Map µPD789425 789435 Special function registers 256 8 bits Internal high speed RAM 512 8 bits LCD display RAM 5 4 bits Reserved Reserved Internal ROM 12288 8 bits FFFFH FF00H FEFFH FD00H FCFFH FA00H F9FFH 0000H Program memory space Data memory space 2FFFH 0000H Program area 0080H 007FH Program area 0040H 003FH CALLT table area 0022H 0021H Vector table area FA05H FA04H 3000H 2FF...

Page 47: ...8 bits Internal high speed RAM 512 8 bits Internal ROM 16384 8 bits FFFFH FF00H FEFFH 0000H Program memory space Data memory space 3FFFH 0000H Program area 0080H 007FH Program area 0040H 003FH CALLT table area 0022H 0021H Vector table area LCD display RAM 5 4 bits Reserved Reserved FD00H FCFFH FA00H F9FFH FA05H FA04H 4000H 3FFFH ...

Page 48: ...its Internal high speed RAM 512 8 bits Flash memory 16384 8 bits FFFFH FF00H FEFFH 0000H Program memory space Data memory space 3FFFH 0000H Program area 0080H 007FH Program area 0040H 003FH CALLT table area 0022H 0021H Vector table area LCD display RAM 5 4 bits Reserved Reserved FD00H FCFFH FA00H F9FFH FA05H FA04H 4000H 3FFFH ...

Page 49: ... bits Internal high speed RAM 512 8 bits Internal ROM 12288 8 bits FFFFH FF00H FEFFH 0000H Program memory space Data memory space 2FFFH 0000H Program area 0080H 007FH Program area 0040H 003FH CALLT table area 0022H 0021H Vector table area LCD display RAM 15 4 bits Reserved Reserved FD00H FCFFH FA00H F9FFH FA0FH FA0EH 3000H 2FFFH ...

Page 50: ... bits Internal high speed RAM 512 8 bits Internal ROM 16384 8 bits FFFFH FF00H FEFFH 0000H Program memory space Data memory space 3FFFH 0000H Program area 0080H 007FH Program area 0040H 003FH CALLT table area 0022H 0021H Vector table area LCD display RAM 15 4 bits Reserved Reserved FD00H FCFFH FA00H F9FFH FA0FH FA0EH 4000H 3FFFH ...

Page 51: ...ts Internal high speed RAM 512 8 bits Flash memory 16384 8 bits FFFFH FF00H FEFFH 0000H Program memory space Data memory space 3FFFH 0000H Program area 0080H 007FH Program area 0040H 003FH CALLT table area 0022H 0021H Vector table area LCD display RAM 15 4 bits Reserved Reserved FD00H FCFFH FA00H F9FFH FA0FH FA0EH 4000H 3FFFH ...

Page 52: ...emory space 1 Vector table area The 34 byte area of addresses 0000H to 0021H is reserved as a vector table area This area stores program start addresses to be used when branching by the RESET input or an interrupt request generation Of a 16 bit program address the lower 8 bits are stored in an even address and the higher 8 bits are stored in an odd address Table 3 2 Vector Table Vector Table Addre...

Page 53: ... is also used as a stack 2 LCD display RAM LCD display RAM is incorporated The LCD display RAM can also be used as ordinary RAM Each subseries incorporates LCD display RAM with the following capacity Table 3 3 LCD Display RAM Capacity Subseries Name Area Capacity µPD789426 789436 Subseries FA00H to FA04H 5 4 bits µPD789446 789456 Subseries FA00H to FA0EH 15 4 bits 3 1 3 Special function register S...

Page 54: ...pond to the particular function an area such as the special function registers are available Figures 3 7 through 3 12 show the data memory addressing modes Figure 3 7 Data Memory Addressing µPD789425 789435 Special function registers SFRs 256 8 bits Internal high speed RAM 512 8 bits Internal ROM 12288 8 bits FFFFH 0000H Direct addressing Register indirect addressing Based addressing FF00H FEFFH F...

Page 55: ...registers SFRs 256 8 bits Internal high speed RAM 512 8 bits Internal ROM 16384 8 bits FFFFH 0000H Direct addressing Register indirect addressing Based addressing FF00H FEFFH FF20H FF1FH FE20H FE1FH SFR addressing Short direct addressing LCD display RAM 5 4 bits Reserved Reserved FD00H FCFFH FA00H F9FFH 4000H 3FFFH FA05H FA04H ...

Page 56: ...isters SFRs 256 8 bits Internal high speed RAM 512 8 bits Flash memory 16384 8 bits FFFFH 0000H Direct addressing Register indirect addressing Based addressing FF00H FEFFH FF20H FF1FH FE20H FE1FH SFR addressing Short direct addressing LCD display RAM 5 4 bits Reserved Reserved FD00H FCFFH FA00H F9FFH 4000H 3FFFH FA05H FA04H ...

Page 57: ...registers SFRs 256 8 bits Internal high speed RAM 512 8 bits Internal ROM 12288 8 bits FFFFH 0000H Direct addressing Register indirect addressing Based addressing FF00H FEFFH FF20H FF1FH FE20H FE1FH SFR addressing Short direct addressing LCD display RAM 15 4 bits Reserved Reserved FD00H FCFFH FA00H F9FFH 3000H 2FFFH FA0FH FA0EH ...

Page 58: ...registers SFRs 256 8 bits Internal high speed RAM 512 8 bits Internal ROM 16384 8 bits FFFFH 0000H Direct addressing Register indirect addressing Based addressing FF00H FEFFH FF20H FF1FH FE20H FE1FH SFR addressing Short direct addressing LCD display RAM 15 4 bits Reserved Reserved FD00H FCFFH FA00H F9FFH 4000H 3FFFH FA0FH FA0EH ...

Page 59: ...isters SFRs 256 8 bits Internal high speed RAM 512 8 bits Flash memory 16384 8 bits FFFFH 0000H Direct addressing Register indirect addressing Based addressing FF00H FEFFH FF20H FF1FH FE20H FE1FH SFR addressing Short direct addressing LCD display RAM 15 4 bits Reserved Reserved FD00H FCFFH FA00H F9FFH 4000H 3FFFH FA0FH FA0EH ...

Page 60: ...umber of bytes of the instruction to be fetched When a branch instruction is executed immediate data or register contents are set RESET input sets the reset vector table values at addresses 0000H and 0001H to the program counter Figure 3 13 Program Counter Configuration 0 15 PC14 PC15 PC PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 2 Program status word PSW The program status word i...

Page 61: ...arious interrupt sources IE is reset 0 upon DI instruction execution or interrupt acknowledgment and is set 1 upon EI instruction execution b Zero flag Z When the operation result is zero this flag is set 1 It is reset 0 in all other cases c Auxiliary carry flag AC If the operation result has a carry from bit 3 or a borrow at bit 3 this flag is set 1 It is reset 0 in all other cases d Carry flag C...

Page 62: ...estores data as shown in Figures 3 16 and 3 17 Caution Since RESET input makes the SP contents undefined be sure to initialize the SP before instruction execution Figure 3 16 Data to Be Saved to Stack Memory Interrupt PSW PC15 to PC8 PC15 to PC8 PC7 to PC0 Lower register pairs SP SP _ 2 SP _ 2 CALL CALLT instructions PUSH rp instruction SP _ 1 SP SP SP _ 2 SP _ 2 SP _ 1 SP PC7 to PC0 SP _ 3 SP _ 2...

Page 63: ...s in pairs can be used as a 16 bit register AX BC DE and HL General purpose registers can be described in terms of function names X A C B E D L H AX BC DE or HL or absolute names R0 to R7 and RP0 to RP3 Figure 3 18 General Purpose Register Configuration a Absolute names R0 15 0 7 0 16 bit processing 8 bit processing RP3 RP2 RP1 RP0 R1 R2 R3 R4 R5 R6 R7 b Function names X 15 0 7 0 16 bit processing...

Page 64: ... operand sfr This manipulation can also be specified with an address 16 bit manipulation Describes a symbol reserved by the assembler for the 16 bit manipulation instruction operand When addressing an address describe an even address Table 3 4 lists the special function registers The meanings of the symbols in this table are as follows Symbol Indicates the addresses of the implemented special func...

Page 65: ...90 Note 2 R Note 3 Undefined FF20H Port mode register 0 PM0 FF21H Port mode register 1 PM1 FF22H Port mode register 2 PM2 FF23H Port mode register 3 PM3 FF25H Port mode register 5 PM5 R W FFH Notes 1 µPD789426 and 789436 Subseries only 2 Name of SFR dedicated for 16 bit access 3 Only in short direct addressing 16 bit access is possible 4 These are 16 bit access dedicated registers however 8 bit ac...

Page 66: ...tor output control register 60 TCA60 W FF70H Asynchronous serial interface mode register 20 ASIM20 R W FF71H Asynchronous serial interface status register 20 ASIS20 R FF72H Serial operation mode register 20 CSIM20 FF73H Baud rate generator control register 20 BRGC20 FF80H A D converter mode register 0 ADM0 FF84H Analog input channel specification register 0 ADS0 FFB0H LCD display mode register 0 L...

Page 67: ...dressing Function The value obtained by adding 8 bit immediate data displacement value jdisp8 of an instruction code to the start address of the following instruction is transferred to the program counter PC and branched The displacement value is treated as signed two s complement data 128 to 127 and bit 7 becomes a sign bit This means that information is relatively branched to a location between ...

Page 68: ...transferred to the program counter PC and branched This function is carried out when the CALL addr16 or BR addr16 instruction is executed CALL addr16 and BR addr16 instructions can be branched to any location in the memory space Illustration In case of CALL addr16 and BR addr16 instructions 15 0 PC 8 7 7 0 CALL or BR Low Addr High Addr ...

Page 69: ...ted The instruction enables a branch to any location in the memory space by referring to the addresses stored in the memory table at 40H to 7FH Illustration 15 1 15 0 PC 7 0 Low Addr High Addr Memory Table Effective address 1 Effective address 0 1 0 0 0 0 0 0 0 0 8 7 8 7 6 5 0 0 0 0 1 7 6 5 1 0 ta4 0 Instruction code 3 3 4 Register addressing Function The register pair AX contents to be specified ...

Page 70: ...nstruction execution 3 4 1 Direct addressing Function The memory indicated with immediate data in an instruction word is directly addressed Operand format Identifier Description addr16 Label or 16 bit immediate data Description example MOV A FE00H When setting addr16 to FE00H Instruction code 0 0 1 0 1 0 0 1 OP code 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 00H FEH Illustration 7 0 OP code addr16 Lower addr...

Page 71: ...r event counter are mapped in this area and these SFRs can be manipulated with a small number of bytes and clocks When 8 bit immediate data is at 20H to FFH bit 8 of an effective address is set to 0 When it is at 00H to 1FH bit 8 is set to 1 See Illustration below Operand format Identifier Description saddr Label or FE20H to FF1FH immediate data saddrp Label or FE20H to FF1FH immediate data even a...

Page 72: ... word This addressing is applied to the 256 byte space FF00H to FFFFH However the SFRs mapped at FF00H to FF1FH can also be accessed with short direct addressing Operand format Identifier Description sfr Special function register name Description example MOV PM0 A When selecting PM0 for sfr Instruction code 1 1 1 0 0 1 1 1 0 0 1 0 0 0 0 0 Illustration 15 0 SFR Effective Address 1 1 1 1 1 1 1 8 7 0...

Page 73: ...rand format is executed When an 8 bit register is specified one of the eight registers is specified with 3 bits in the instruction code Operand format Identifier Description r X A C B E D L H rp AX BC DE HL r and rp can be described with absolute names R0 to R7 and RP0 to RP3 as well as function names X A C B E D L H AX BC DE and HL Description example MOV A C When selecting the C register for r I...

Page 74: ...The register pair to be accessed is specified by the register pair specification code in an instruction code This addressing can be carried out for all the memory spaces Operand format Identifier Description DE HL Description example MOV A DE When selecting register pair DE Instruction code 0 0 1 0 1 0 1 1 Illustration 15 0 8 D 7 E 0 7 7 0 A DE Addressed memory contents are transferred Memory addr...

Page 75: ...s Operand format Identifier Description HL byte Description example MOV A HL 10H When setting byte to 10H Instruction code 0 0 1 0 1 1 0 1 0 0 0 1 0 0 0 0 3 4 7 Stack addressing Function The stack area is indirectly addressed with the stack pointer SP contents This addressing method is automatically employed when the PUSH POP subroutine call and return instructions are executed or the register is ...

Page 76: ...ous methods of control Numerous other functions are provided that can be used in addition to the digital I O port functions For more information on these additional functions see CHAPTER 2 PIN FUNCTIONS Figure 4 1 Port Types µPD789426 789436 Subseries P30 P33 P60 P00 P03 P10 P11 Port 1 Port 2 Port 3 Port 5 P20 P26 P65 Port 0 Port 6 P70 P72 Port 8 Port 7 P80 P81 P90 P97 Port 9 P50 P53 ...

Page 77: ...TER 4 PORT FUNCTIONS User s Manual U15075EJ2V1UD 77 Figure 4 2 Port Types µPD789446 789456 Subseries P30 P33 P60 P00 P03 P10 P11 Port 1 Port 2 Port 3 P20 P26 P65 Port 0 P70 P72 Port 7 Port 6 P50 P53 Port 5 ...

Page 78: ... port Input output can be specified in 1 bit units When used as an input port an on chip pull up resistor can be specified by setting pull up resistor option register B2 PUB2 Input TO90 P30 INTP0 CPT90 P31 INTP1 TO50 TMI60 P32 INTP2 TO60 P33 I O Port 3 4 bit I O port Input output can be specified in 1 bit units When used as an input port an on chip pull up resistor can be specified by setting pull...

Page 79: ...specified by setting pull up resistor option register B9 PUB9 Input Note µPD789426 789436 Subseries only 4 2 Port Configuration Ports have the following hardware configuration Table 4 2 Configuration of Port Item Configuration Control registers Port mode register PMm m 0 to 3 5 7 to 9 Pull up resistor option register PU0 PUB2 PUB3 PUB7 to PUB9 µPD789426 789436 Subseries Total 40 CMOS I O 30 CMOS i...

Page 80: ... connected in 4 bit units by setting pull up resistor option register 0 PU0 Port 0 is set in the input mode when the RESET signal is input Figure 4 3 shows a block diagram of port 0 Figure 4 3 Block Diagram of P00 to P03 WRKRM00 VDD P00 KR0 to P03 KR3 WRPUO RD WRPORT WRPM PU00 PM00 to PM03 KRM000 P ch Internal bus Selector Output latch P00 to P03 Alternate function KRM00 Key return mode register 0...

Page 81: ...pins on chip pull up resistors can be connected in 2 bit units by setting pull up resistor option register 0 PU0 This port is set in the input mode when the RESET signal is input Figure 4 4 shows a block diagram of port 1 Figure 4 4 Block Diagram of P10 and P11 PU0 Pull up resistor option register 0 PM Port mode register RD Port 1 read signal WR Port 1 write signal WRPU0 RD WRPORT WRPM PU01 PM10 P...

Page 82: ...l interface I O buzzer output and timer output This port is set in the input mode when the RESET signal is input Figures 4 5 to 4 10 show block diagrams of port 2 Caution When using the pins of port 2 as the serial interface the I O or output latch must be set according to the function to be used For how to set the latches see Figure 12 2 Settings of Serial Interface 20 Operating Mode Figure 4 5 B...

Page 83: ...lock Diagram of P21 and P26 Internal bus VDD P ch P21 BZO90 P26 TO90 WRPUB2 RD WRPORT WRPM PUB21 PUB26 Output latch P21 P26 PM21 PM26 Alternate function Selector PUB2 Pull up resistor option register B2 PM Port mode register RD Port 2 read signal WR Port 2 write signal ...

Page 84: ...D 84 Figure 4 7 Block Diagram of P22 Internal bus VDD P ch P22 SS20 WRPUB2 RD WRPORT WRPM PUB22 Alternate function Output latch P22 PM22 Selector PUB2 Pull up resistor option register B2 PM Port mode register RD Port 2 read signal WR Port 2 write signal ...

Page 85: ...8 Block Diagram of P23 Internal bus VDD P ch P23 ASCK20 SCK20 WRPUB2 RD WRPORT WRPM PUB23 Alternate function Output latch P23 PM23 Alternate function Selector PUB2 Pull up resistor option register B2 PM Port mode register RD Port 2 read signal WR Port 2 write signal ...

Page 86: ...re 4 9 Block Diagram of P24 PUB2 Pull up resistor option register B2 PM Port mode register RD Port 2 read signal WR Port 2 write signal Internal bus VDD P24 SO20 TxD20 WRPUB2 RD WRPORT WRPM PUB24 Alternate function Output latch P24 PM24 Selector P ch SS20 output ...

Page 87: ... Figure 4 10 Block Diagram of P25 P25 SI20 RxD20 WRPUB2 RD WRPORT WRPM PUB25 Alternate function Output latch P25 PM25 VDD P ch Internal bus Selector PUB2 Pull up resistor option register B2 PM Port mode register RD Port 2 read signal WR Port 2 write signal ...

Page 88: ...it units by setting pull up resistor option register B3 PUB3 This port is also used as an external interrupt input capture input and timer I O This port is set in the input mode when the RESET signal is input Figures 4 11 and 4 12 show block diagrams of port 3 Figure 4 11 Block Diagram of P30 P30 INTP0 CPT90 WRPUB3 RD WRPORT WRPM PUB30 PM30 VDD P ch Internal bus Alternate function Selector Output ...

Page 89: ...B3 Pull up resistor option register B3 PM Port mode register RD Port 3 read signal WR Port 3 write signal P31 INTP1 TO50 TMI60 P32 INTP2 TO60 P33 INTP3 TO61 WRPUB3 RD WRPORT WRPM PUB31 to PUB33 PM31 to PM33 VDD P ch Internal bus Alternate function Selector Output latch P31 to P33 Alternate function ...

Page 90: ...ip pull up resistor can be specified by a mask option This port is set in the input mode when the RESET signal is input Figure 4 13 shows a block diagram of port 5 Figure 4 13 Block Diagram of P50 to P53 Internal bus Selector RD PM50 to PM53 P50 to P53 N ch WRPORT Output latch P50 to P53 WRPM VDD Mask option resistor Mask ROM version only For flash memory version a pull up resistor is not incorpor...

Page 91: ...1UD 91 4 2 6 Port 6 This is a 6 bit input only port This port is also used as the analog input of an A D converter Figure 4 14 shows a block diagram of Port 6 Figure 4 14 Block Diagram of Port 6 VREF RD A D converter P60 ANI0 to P65 ANI5 Internal bus ...

Page 92: ...pull up resistors can be connected in 1 bit units by setting pull up resistor option register B7 PUB7 This port is set in the input mode when the RESET signal is input Figure 4 15 shows a block diagram of Port 7 Figure 4 15 Block Diagram of P70 to P72 WRPUB7 RD WRPORT WRPM PUB70 to PUB72 Output latch P70 to P72 PM70 to PM72 VDD P ch P70 to P72 Internal bus Selector PUB7 Pull up resistor option reg...

Page 93: ...t port pins on chip pull up resistors can be connected in 1 bit units by setting pull up resistor option register B8 PUB8 This port is set in the input mode when the RESET signal is input Figure 4 16 shows a block diagram of port 8 Figure 4 16 Block Diagram of P80 and P81 PUB8 Pull up resistor option register B8 PM Port mode register RD Port 8 read signal WR Port 8 write signal WRPUB8 RD WRPORT WR...

Page 94: ...port pins on chip pull up resistors can be connected in 1 bit units by setting pull up resistor option register B9 PUB9 This port is set in the input mode when the RESET signal is input Figure 4 17 shows a block diagram of port 9 Figure 4 17 Block Diagram of P90 to P97 WRPUB9 RD WRPORT WRPM PUB90 to PUB97 Output latch P90 to P97 PM90 to PM97 VDD P ch P90 to P97 Internal bus Selector PUB9 Pull up r...

Page 95: ...input output in 1 bit units The port mode registers are independently set with a 1 bit or 8 bit memory manipulation instruction RESET input sets the registers to FFH When port pins are used as alternate function pins set the port mode register and output latch according to Table 4 3 Caution As port 3 has an alternate function as external interrupt input when the port function output mode is specif...

Page 96: ...7 Symbol Address After reset 6 5 4 3 2 1 0 R W FF20H FF21H FF25H FFH FFH FFH R W R W R W 1 1 1 1 1 PM72 PM71 PM70 PM7 FF27H FFH R W 1 1 1 1 1 1 PM81 PM80 PM8Note FF28H FFH R W PM97 PM96 PM95 PM94 PM93 PM92 PM91 PM90 PM9Note FF29H FFH R W 1 1 PM26 1 PM25 1 PM24 1 PM23 PM33 PM22 PM32 PM21 PM31 PM20 PM30 PM2 PM3 FF22H FF23H FFH FFH R W R W Pmn pin input output mode selection m 0 to 3 5 7 to 9 n 0 to ...

Page 97: ...ort output latch 2 Pull up resistor option register 0 PU0 Pull up resistor option register 0 PU0 sets whether on chip pull up registers are used on ports 0 and 1 or not On the port specified to use an on chip pull up resistor by PU0 the pull up resistor can be internally used only for the bits set in the input mode No on chip pull up resistors can be used for the bits set in the output mode regard...

Page 98: ...Address After reset R W FF32H 00H R W 7 6 5 4 3 2 1 0 PUB2n 0 1 On chip pull up resistor not used On chip pull up resistor used Symbol 4 Pull up resistor option register B3 PUB3 Pull up resistor option register B3 PUB3 sets whether on chip pull up resistors on P30 to P33 are used or not On the port specified to use an on chip pull up resistor by PUB3 the pull up resistor can be internally used onl...

Page 99: ...W 7 6 5 4 3 2 1 0 PUB7n 0 1 On chip pull up resistor not used On chip pull up resistor used Symbol 6 Pull up resistor option register B8 PUB8 Note Pull up resistor option register B8 PUB8 sets whether on chip pull up resistors on P80 and P81 are used or not On the port specified to use an on chip pull up resistor by PUB8 the pull up resistor can be internally used only for bits set in the input mo...

Page 100: ...be used for the bits set in the output mode regardless of the setting of PUB9 This also applies to when the pins are used for alternate function PUB9 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets PUB9 to 00H Note Incorporated only in the µPD789426 and 789436 Subseries Figure 4 24 Format of Pull Up Resistor Option Register B9 P9n on chip pull up resistor selection n ...

Page 101: ... the pin that is set in the input mode and not subject to manipulation become undefined 4 4 2 Reading from I O port 1 In output mode The status of an output latch can be read by using a transfer instruction The contents of the output latch are not changed 2 In input mode The status of a pin can be read by using a transfer instruction The contents of the output latch are not changed 4 4 3 Arithmeti...

Page 102: ...TOP instruction or setting the processor clock control register PCC Main system clock oscillator RC oscillation mask option This circuit oscillates a frequency of 2 0 to 4 0 MHz Oscillation can be stopped by executing the STOP instruction or setting the processor clock control register PCC Subsystem clock oscillator This circuit oscillates a frequency of 32 768 kHz Oscillation can be stopped by th...

Page 103: ... 8 bit timer 60 Watch timer LCD controller driver Clock to peripheral hardware CPU clock fCPU Standby controller Wait controller Selector STOP MCC PCC1 CLS CSS0 Internal bus Suboscillation mode register SCKM FRC SCC Internal bus Subclock control register CSS Processor clock control register PCC Subsystem clock oscillator X1 or CL1 X2 or CL2 XT1 XT2 Main system clock oscillator ...

Page 104: ... s Manual U15075EJ2V1UD 104 5 3 Registers Controlling Clock Generator The clock generator is controlled by the following registers Processor clock control register PCC Suboscillation mode register SCKM Subclock control register CSS ...

Page 105: ...µ µ µ Note The CPU clock is selected according to a combination of the PCC1 flag in the processor clock control register PCC and the CSS0 flag in the subclock control register CSS Refer to 5 3 3 Subclock control register CSS Cautions 1 Bits 0 and 2 to 6 must be set to 0 2 The MCC can be set only when the subsystem clock has been selected as the CPU clock Remarks 1 fX Main system clock oscillation ...

Page 106: ...r selectionNote 0 0 0 0 0 0 FRC SCC SCKM Symbol Address After reset R W FFF0H 00H R W 7 6 5 4 3 2 1 0 FRC 0 1 On chip feedback resistor used On chip feedback resistor not used Control of subsystem clock oscillator operation SCC 0 1 Operation enabled Operation disabled Note The feedback resistor is necessary to adjust the bias point of the oscillation waveform to close to the mid point of the suppl...

Page 107: ...o 00H Figure 5 4 Format of Subclock Control Register CPU clock operation status 0 0 CLS CSS0 0 0 0 0 CSS Address After reset R W FFF2H 00H R W 7 6 5 4 3 2 1 0 CLS 0 1 Operation based on the output of the divided main system clock Operation based on the subsystem clock Selection of the main system or subsystem clock oscillator CSS0 0 1 Divided output from the main system clock oscillator Output fro...

Page 108: ...e external circuit of the main system clock oscillator crystal ceramic oscillation Figure 5 5 External Circuit of Main System Clock Oscillator Crystal Ceramic Oscillation a Crystal or ceramic oscillation b External clock Crystal or ceramic resonator VSS X2 X1 External clock X1 X2 Caution When using the main system or subsystem clock oscillator wire as follows in the area enclosed by the broken lin...

Page 109: ...to the XT1 pin and input the inverted signal to the XT2 pin Figure 5 7 shows the external circuit of the subsystem clock oscillator Figure 5 7 External Circuit of Subsystem Clock Oscillator a Crystal oscillation b External clock XT2 VSS XT1 32 768 kHz Crystal resonator External clock XT1 XT2 Caution When using the main system or subsystem clock oscillator wire as follows in the area enclosed by th...

Page 110: ...les of Incorrect Connection for Crystal Ceramic Oscillation 1 2 a Too long wiring b Crossed signal line VSS X1 X2 VSS X1 X2 PORTn n 0 to 3 5 to 9 c Wiring near high fluctuating current d Current flowing through ground line of oscillator potential at points A B and C fluctuates VSS X1 X2 High current VSS X1 A B C Pmn VDD High current X2 Remark When using the subsystem clock read X1 and X2 as XT1 an...

Page 111: ...075EJ2V1UD 111 Figure 5 8 Examples of Incorrect Connection for Crystal Ceramic Oscillation 2 2 e Signal is fetched VSS X1 X2 Remark When using the subsystem clock read X1 and X2 as XT1 and XT2 respectively and connect a resistor to XT2 in series ...

Page 112: ...ure 5 9 Examples of Incorrect Connection for RC Oscillation 1 3 a Too long wiring Main system clock Subsystem clock VSS CL2 CL1 XT1 XT2 VSS b Crossed signal line Main system clock Subsystem clock VSS CL2 PORTn n 0 to 3 5 to 9 CL1 PORTn n 0 to 3 5 to 9 XT1 XT2 VSS ...

Page 113: ...fluctuating current Main system clock Subsystem clock VSS CL2 CL1 High current XT1 XT2 VSS High current d Current flowing through ground line of oscillator potential at points A B and C fluctuates Main system clock Subsystem clock VSS VDD CL2 CL1 PORTn n 0 to 3 5 7 to 9 A B High current VDD PORTn n 0 to 3 5 7 to 9 XT1 XT2 VSS A B C High current ...

Page 114: ...hen no subsystem clock is used If a subsystem clock is not necessary for example for low power consumption operation or clock operation handle the XT1 and XT2 pins as follows XT1 Connect to VSS XT2 Leave open In this case however a small current leaks via the on chip feedback resistor in the subsystem clock oscillator when the main system clock is stopped To avoid this set bit 1 FRC of the subosci...

Page 115: ... clock selected In a system where no subsystem clock is used setting bit 1 FRC of the SCKM so that the on chip feedback resistor cannot be used reduces power consumption in STOP mode In a system where a subsystem clock is used setting SCKM bit 0 to 1 can cause the subsystem clock to stop oscillation d CSS bit 4 CSS0 can be used to select the subsystem clock so that low current consumption operatio...

Page 116: ...hing Set Value After Switching CSS0 PCC1 CSS0 PCC1 CSS0 PCC1 CSS0 PCC1 0 0 0 1 1 x 0 0 4 clocks 2fX fXT clocks 306 clocks 1 2 clocks fX 2fXT clocks 76 clocks 1 x 2 clocks 2 clocks Remarks 1 Two clocks are the minimum instruction execution time of the CPU clock before switching 2 The parenthesized values apply to operation at fX 5 0 MHz or fXT 32 768 kHz 3 x don t care Table 5 3 Maximum Time Requir...

Page 117: ...truction execution at the slow speed of the main system clock 1 6 µs at 5 0 MHz operation 2 After the time required for the VDD voltage to rise to the level at which the CPU can operate at high speed has elapsed bit 1 PCC1 of the processor clock control register PCC and bit 4 CSS0 of the subclock control register CSS are rewritten so that high speed operation can be selected 3 A drop of the VDD vo...

Page 118: ...main system clock 2 0 µs at 4 0 MHz operation 2 After the time required for the VDD voltage to rise to the level at which the CPU can operate at high speed has elapsed bit 1 PCC1 of the processor clock control register PCC and bit 4 CSS0 of the subclock control register CSS are rewritten so that high speed operation can be selected 3 A drop of the VDD voltage is detected with an interrupt request ...

Page 119: ... 1 Timer interrupt An interrupt is generated when a count value and compare value matches 2 Timer output Timer output can be controlled when a count value and compare value matches 3 Buzzer output Buzzer output can be controlled by software 4 Count value capture A count value of 16 bit timer counter 90 TM90 is latched into a capture register synchronizing with the capture trigger and retained ...

Page 120: ...rdware Table 6 1 16 Bit Timer 90 Configuration Item Configuration Timer counters 16 bits 1 TM90 Registers Compare register 16 bits 1 CR90 Capture register 16 bits 1 TCP90 Timer outputs 1 TO90 Control registers 16 bit timer mode control register 90 TMC90 Buzzer output control register 90 BZC90 Port mode registers 2 3 PM2 PM3 Port 2 P2 ...

Page 121: ...nter 90 TM90 16 bit compare register 90 CR90 fX 22 fX 26 fX 27 fXT CPT90 INTP0 P30 TOC90 TCL901TCL900 TOE90 F F TOD90 P26 Output latch P21 Output latch PM26 PM21 TO90 P26 INTTM90 BZO90 P21 Match OVF Buzzer output control register BZC90 3 BCS902 BCS901 BCS900BZOE90 Edge detector Synchronization circuit fX Write controller Write controller fX 2 CPU clock Selector Selector Selector Figure 6 1 Block D...

Page 122: ...TM90 TM90 is used to count the number of pulses The contents of TM90 are read with an 8 bit or 16 bit memory manipulation instruction RESET input sets TM90 to 0000H Cautions 1 The count becomes undefined when STOP mode is deselected because the count operation is performed before oscillation stabilizes 2 TM90 is designed to be manipulated with a 16 bit memory manipulation instruction However it ca...

Page 123: ... bit timer mode control register 90 TMC90 Buzzer output control register 90 BZC90 Port mode registers 2 3 PM2 PM3 Port 2 P2 1 16 bit timer mode control register 90 TMC90 16 bit timer mode control register 90 TMC90 controls the setting of a count clock capture edge etc TMC90 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets TMC90 to 00H ...

Page 124: ... 0 1 Timer output data inversion control Inversion disabled Inversion enabled TCL901 0 0 1 1 16 bit timer counter 90 count clock selection TCL900 0 1 0 1 TOE90 0 1 16 bit timer counter 90 output control Output disabled port mode Output enabled TOD90 0 1 Timer output data Timer output data is 0 Timer output data is 1 fX 22 1 25 MHz fX 26 78 1 kHz fX 27 39 1 kHz fXT 32 768 kHz Note Bit 7 is read onl...

Page 125: ...8 4 88 kHz fcl 29 2 44 kHz fcl 210 1 22 kHz fcl 211 610 Hz fcl 212 305 Hz fcl 213 153 Hz fcl 24 4 88 kHz fcl 25 2 44 kHz fcl 28 305 Hz fcl 29 153 Hz fcl 210 76 Hz fcl 211 38 Hz fcl 212 19 Hz fcl 213 10 Hz fcl 24 2 44 kHz fcl 25 1 22 kHz fcl 28 153 Hz fcl 29 76 Hz fcl 210 38 Hz fcl 211 19 Hz fcl 212 10 Hz fcl 213 5 Hz fcl 24 2 05 kHz fcl 25 1 02 kHz fcl 28 128 Hz fcl 29 64 Hz fcl 210 32 Hz fcl 211 ...

Page 126: ...d PM26 to 0 When using the P30 INTP0 CPT90 pin as a capture input set PM30 to 1 PM2 and PM3 are set with a 1 bit or 8 bit memory manipulation instruction RESET input sets PM2 and PM3 to FFH Figure 6 4 Format of Port Mode Registers 2 3 PMmn Pmn pin I O mode mn 20 to 26 30 to 33 Output mode output buffer ON Input mode output buffer OFF 0 1 1 1 1 1 PM33 PM32 PM31 PM30 PM3 Symbol Address After reset R...

Page 127: ... to 0 the capture operation is prohibited When the count value of 16 bit timer counter 90 TM90 matches the value set in CR90 counting of TM90 continues and an interrupt request signal INTTM90 is generated Table 6 2 shows interval time and Figure 6 6 shows timing of timer interrupt operation Caution When rewriting the value in CR90 during a count operation be sure to execute the following processin...

Page 128: ...J2V1UD 128 Figure 6 6 Timing of Timer Interrupt Operation CR90 TM90 count value Count clock INTTM90 TO90 TOF90 N N N N N t 0000H N FFFFH N 0000H 0001H 0001H Interrupt acknowledgment Interrupt acknowledgment Overflow flag set Remark N 0000H to FFFFH ...

Page 129: ...0 1 0 1 0 1 1 0 1 0 1 1 TOD90 TOF90 CPT901 CPT900 TOC90 TCL901 TCL900 TOE90 TMC90 Setting of count clock see Table 6 2 Inverse enable of timer output data TO90 output enable Caution If both the CPT901 flag and CPT900 flag are set to 0 the capture operation is prohibited When the count value of 16 bit timer counter 90 TM90 matches the value set in CR90 the output status of the TO90 P26 pin is inver...

Page 130: ... detected and latches and retains the count value of 16 bit timer register 90 The TCP90 fetches the count value within 2 clocks and retains the count value until the next capture edge detection Table 6 3 and Figure 6 10 show the settings of the capture edge and the capture operation timing respectively Table 6 3 Settings of Capture Edge CPT901 CPT900 Capture Edge Selection 0 0 Capture operation pr...

Page 131: ...TM90 to 0000H and TM90 starts free running Figure 6 11 shows the timing of 16 bit timer counter 90 readout Cautions 1 The count value after releasing stop becomes undefined because the count operation is executed during the oscillation stabilization time 2 Though TM90 is designed for a 16 bit transfer instruction an 8 bit transfer instruction can also be used When using an 8 bit transfer instructi...

Page 132: ...quency see Table 6 4 Enables buzzer output Table 6 4 Buzzer Frequency of 16 Bit Timer 90 Buzzer Frequency BCS902 BCS901 BCS900 fcl fX 2 2 fcl fX 2 6 fcl fX 2 7 fcl fXT 0 0 0 fcl 2 4 78 1 kHz fcl 2 4 4 88 kHz fcl 2 4 2 44 kHz fcl 2 4 2 05 kHz 0 0 1 fcl 2 5 39 1 kHz fcl 2 5 2 44 kHz fcl 2 5 1 22 kHz fcl 2 5 1 02 kHz 0 1 0 fcl 2 8 4 88 kHz fcl 2 8 305 Hz fcl 2 8 153 Hz fcl 2 8 128 Hz 0 1 1 fcl 2 9 2 ...

Page 133: ...hen the main system clock is stopped 2 The read function of TM90 uses the CPU clock for control refer to Figure 6 1 and reads an undefined value when the CPU clock is slower than the count clock values are not guaranteed When reading TM90 set the count clock to the same speed as the CPU clock when the CPU clock is the main system clock high speed mode is set or select a clock slower than the CPU c...

Page 134: ... Main system clock Oscillation stopped BZOE90 1 Buzzer output enabled At this time when the setting of P21 the buzzer output alternate function pin is PM21 0 P21 0 a square wave of the buzzer frequency is output from P21 To avoid outputting the buzzer frequency make either of the following settings Set P21 to input mode PM21 1 If P21 cannot be set to input mode set the port latch value of P21 to 1...

Page 135: ...bits first 3 Next rewrite the lower byte of CR90 16 bits 4 Clear the interrupt request flag TMIF90 5 After more than half the cycle of the count clock has passed from the start of the interrupt enable timer interrupts and timer output inversion Program example A When count clock 64 fX CPU clock fX TM90_VCT SET1 TMMK90 Timer interrupt disable 6 clocks CLR1 TMC90 3 Timer output inversion disable 6 c...

Page 136: ...tput inversion Program example B When count clock 64 fX CPU clock fX TM90_VCT SET1 TMMK90 Timer interrupt disable CLR1 TMC90 3 Timer output inversion disable MOVW AX xxyyH CR90 rewrite value setting MOVW CR90 AX CR90 rewriting NOP NOP NOP NOP CLR1 TMIF90 Interrupt request flag clearing CLR1 TMMK90 Timer interrupt enable SET1 TMC90 3 Timer output inversion enable Note Wait for more than one cycle o...

Page 137: ...1 8 bit timer counter mode discrete mode The following functions can be used in this mode Interval timer with 8 bit resolution External event counter with 8 bit resolution timer 40 only Square wave output with 8 bit resolution 2 16 bit timer counter mode cascade connection mode Operation as a 16 bit timer event counter is enabled during cascade connection mode The following functions can be used i...

Page 138: ...imer output pin using software 7 2 8 Bit Timers 50 60 Configuration 8 bit timers 50 and 60 include the following hardware Table 7 2 8 Bit Timer Configuration Item Configuration Timer counters 8 bits 2 TM50 TM60 Registers Compare registers 8 bits 3 CR50 CR60 CRH60 Timer outputs 3 TO50 TO60 TO61 Control registers 8 bit timer mode control register 50 TMC50 8 bit timer mode control register 60 TMC60 C...

Page 139: ... 27 Timer 60 interrupt request signal from Figure 7 2 B Carrier clock in carrier generator mode or timer 60 output signal in a mode other than carrier generator mode from Figure 7 2 C Cascade connection mode Match Internal bus OVF Bit 7 of TM60 from Figure 7 2 A TOE50 P31 output latch PM31 To Figure 7 2 F Timer 50 match signal in cascade connection mode TO50 TMI60 INTP1 P31 TCE50 TCL502 fX fXT TMD...

Page 140: ...er 60 TCA60 TO61 INTP3 P33 Prescaler Selector Count operation start signal to timer 50 in cascade connection mode To Figure 7 1 D TM50 match signal in cascade connection mode TM60 timer counter match signal in cascade connection mode From Figure 7 1 F To Figure 7 1 E count clock input signal to TM50 To Figure 7 1 A Bit 7 of TM60 in cascade connection mode To Figure 7 1 C Carrier clock during carri...

Page 141: ...write the CR50 with the TOE50 in a cleared status 2 If the valid edge of the count clock is selected for both edges in the PWM output mode TEG50 1 do not set 00H 01H and FFH to the CR50 If the rising edge is selected TEG50 0 do not set 00H to CR50 2 8 bit compare register 60 CR60 This 8 bit register is used to continually compare the value set to CR60 with the count value in 8 bit timer counter 60...

Page 142: ... value overflows ii TM60 After reset When TCE60 bit 7 of 8 bit timer mode control register 60 TMC60 is cleared to 0 When a match occurs between TM60 and CR60 When the TM60 count value overflows b Cascade connection mode TM50 and TM60 are simultaneously cleared to 00H After reset When the TCE60 flag is cleared to 0 When matches occur simultaneously between TM50 and CR50 and between TM60 and CR60 Wh...

Page 143: ...tput mode i TM50 After reset When the TCE50 flag is cleared to 0 When a match occurs between TM50 and CR50 When the TM50 count value overflows ii TM60 Reset When the TCE60 flag is cleared to 0 When a match occurs between TM60 and CRH60 When the TM60 count value overflows ...

Page 144: ...er 50 TMC50 8 bit timer mode control register 60 TMC60 Carrier generator output control register 60 TCA60 Port mode register 3 PM3 Port 3 P3 1 8 bit timer mode control register 50 TMC50 8 bit timer mode control register 50 TMC50 is used to control the timer 50 count clock setting and the operation mode setting TMC50 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets TMC5...

Page 145: ...kHz 0 1 0 fX 2 7 39 1 kHz 0 1 1 fXT 32 768 kHz 1 0 0 Timer 60 match signal 1 0 1 Carrier clock in carrier generator mode or timer 60 output signal in a mode other than carrier generator mode Other than above Setting prohibited TMD501 TMD500 TMD601 TMD600 Selection of operation mode for timer 50 and timer 60 Note 3 0 0 0 0 Discrete mode 8 bit timer counter mode 0 1 0 1 Cascade connection mode 16 bi...

Page 146: ...cascade connection mode the output signal of timer 60 is forcibly selected as the count clock 2 When operating TMC50 be sure to perform settings in the following order 1 Stop TM50 count operation 2 Set the operation mode and the count clock 3 Start count operation Remarks 1 fX Main system clock oscillation frequency ceramic crystal oscillation 2 fCC Main system clock oscillation frequency RC oscil...

Page 147: ...rnal input clock Other than above Setting prohibited TMD501 TMD500 TMD601 TMD600 Selection of operation mode for timer 50 and timer 60 Note 2 0 0 0 0 Discrete mode 8 bit timer counter mode 0 1 0 1 Cascade connection mode 16 bit timer counter mode 0 0 1 1 Carrier generator mode 0 0 1 0 Timer 50 Discrete mode 8 bit counter mode Timer 60 PWM pulse generator mode 1 0 1 0 Timer 50 PWM free running mode...

Page 148: ...y manipulation instruction RESET input sets TCA60 to 00H Figure 7 6 Format of Carrier Generator Output Control Register 60 Symbol 7 6 5 4 3 2 1 0 Address After reset R W TCA60 0 0 0 0 0 RMC60 NRZB60 NRZ60 FF4FH 00H W RMC60 Control of remote control output 0 When NRZB60 1 a carrier pulse is output When NRZB60 0 a low level is output 1 When NRZB60 1 high level signal is output When NRZB60 0 a low le...

Page 149: ...t clock and then rewrite TCA60 7 To enable operation in the carrier generator mode set a value to the compare registers CR50 CR60 and CRH60 and input the necessary value to the NRZB60 and NRZ60 flags in advance Otherwise the signal of the timer match circuit will become unstable and the NRZ60 flag will be undefined 4 Port mode register 3 PM3 This register is used to set the I O mode of port 3 in 1...

Page 150: ...o operate 8 bit timer n0 as an interval timer settings must be made in the following sequence 1 Disable operation of 8 bit timer counter n0 TMn0 TCEn0 0 2 Disable timer output of TOn0 TOEn0 0 3 Set a count value in CRn0 4 Set the operation mode of timer n0 to 8 bit timer counter mode see Figures 7 4 and 7 5 5 Set the count clock for timer n0 see Tables 7 3 and 7 4 6 Enable the operation of TMn0 TC...

Page 151: ...le of timer 60 output Input cycle of timer 60 output 2 8 Input cycle of timer 60 Remarks 1 fX Main system clock oscillation frequency 2 fXT Subsystem clock oscillation frequency Table 7 4 Interval Time of Timer 60 TCL602 TCL601 TCL600 Minimum Interval Time Maximum Interval Time Resolution 0 0 0 1 fX 0 2 µs 2 8 fX 51 2 µs 1 fX 0 2 µs 0 0 1 2 2 fX 0 8 µs 2 10 fX 2 04 ms 2 2 fX 0 8 µs 0 1 0 fTMI inpu...

Page 152: ... 01H N 00H 00H 01H 00H 01H Clear Clear Clear Count start Interrupt acknowledgement Interrupt acknowledgement Interrupt acknowledgement Interval time Interval time Interval time Remarks 1 Interval time N 1 t N 00H to FFH 2 n 5 6 nm 50 60 61 Figure 7 9 Timing of Interval Timer Operation with 8 Bit Resolution When CRn0 Is Set to 00H Count clock CRn0 TCEn0 INTTMn0 TOnm 00H TMn0 00H Count start Remark ...

Page 153: ...00H 01H 00H 01H 00H FFH 00H 01H FFH FFH 00H Clear Clear Clear Count start Remark n 5 6 nm 50 60 61 Figure 7 11 Timing of Interval Timer Operation with 8 Bit Resolution When CRn0 Changes from N to M N M Count clock CRn0 TCEn0 INTTMn0 TOnm TMn0 N 00H 00H N 00H 01H 00H 01H M N M N M Clear Clear Clear Count start Interrupt acknowledgement Interrupt acknowledgement CRn0 overwritten Remark n 5 6 nm 50 6...

Page 154: ...r Clear Clear TMn0 overflows because M N CRn0 overwritten Remark n 5 6 nm 50 60 61 Figure 7 13 Timing of Interval Timer Operation with 8 Bit Resolution When Timer 60 Match Signal Is Selected for Timer 50 Count Clock Timer 60 count clock CR60 TCE60 INTTM60 TO60 TM60 N 00H M 00H 00H 01H M N M 00H M 00H 00H 01H Y 1 Y 00H Y 00H Y Input clock to timer 50 timer 60 match signal TO50 INTTM50 TCE50 CR50 TM...

Page 155: ...7 5 5 Set the operation mode of timer 60 to 8 bit timer counter mode see Figures 7 4 and 7 5 6 Set a count value in CR60 7 Enable the operation of TM60 TCE60 1 Each time the valid edge is input the value of TM60 is incremented When the count value of TM60 matches the value set in CR60 TM60 is cleared to 00H and continues counting At the same time an interrupt request signal INTTM60 is generated Fi...

Page 156: ...ared to 00H and continues counting At the same time an interrupt request signal INTTMn0 is generated The square wave output is cleared to 0 by setting TCEn0 to 0 Tables 7 5 and 7 6 show the square wave output range and Figure 7 15 shows the timing of square wave output Note In the case of timer 60 either TO60 or TO61 can be selected as the timer output pin If TO61 is selected set TOE61 1 Caution B...

Page 157: ...TMI 2 input cycle 2 8 fTMI 2 input cycle 1 0 0 fTMI 2 2 input cycle fTMI 2 2 input cycle 2 8 fTMI 2 2 input cycle 1 0 1 fTMI 2 3 input cycle fTMI 2 3 input cycle 2 8 fTMI 2 3 input cycle Remark fX Main system clock oscillation frequency Figure 7 15 Timing of Square Wave Output with 8 Bit Resolution Count clock CRn0 TCEn0 INTTMn0 TOnmNote N TMn0 N 00H 01H N 00H 01H N 00H 01H 00H 01H Clear Clear Cle...

Page 158: ...owing sequence 1 Disable operation of 8 bit timer counter 50 TM50 and 8 bit timer counter 60 TM60 TCE50 0 TCE60 0 2 Disable timer output of TO60 TOE60 0 3 Set the count clock for timer 60 see Table 7 7 4 Set the operation mode of timer 50 and timer 60 to 16 bit timer counter mode see Figures 7 4 and 7 5 5 Set a count value in CR50 and CR60 6 Enable the operation of TM50 and TM60 TCE60 1Note Note S...

Page 159: ... 1 fX 0 2 µs 2 16 fX 13 1 ms 1 fX 0 2 µs 0 0 1 2 2 fX 0 8 µs 2 18 fX 52 4 ms 2 2 fX 0 8 µs 0 1 0 fTMI input cycle fTMI input cycle 2 16 fTMI input cycle 0 1 1 fTMI 2 input cycle fTMI 2 input cycle 2 16 fTMI 2 input cycle 1 0 0 fTMI 2 2 input cycle fTMI 2 2 input cycle 2 16 fTMI 2 2 input cycle 1 0 1 fTMI 2 3 input cycle fTMI 2 3 input cycle 2 16 fTMI 2 3 input cycle Remark fX Main system clock osc...

Page 160: ...pulse TM50 00H X X 1 01H CR50 X X X 7FH 80H FFH 00H N 00H N N N X X 1 00H t Not cleared because TM50 does not match Cleared because TM50 and TM60 match simultaneously Count start Interrupt not generated because TM50 does not match Interrupt acknowledgement Interrupt acknowledgement Remark Interval time 256X N 1 t X 00H to FFH N 00H to FFH Figure 7 16 Timing of Interval Timer Operation with 16 Bit ...

Page 161: ...er 50 and timer 60 to 16 bit timer counter mode see Figures 7 4 and 7 5 6 Set a count value in CR50 and CR60 7 Enable the operation of TM50 and TM60 TCE60 1Note Note Start and clear of the timer in the 16 bit timer counter mode are controlled by TCE60 the value of TCE50 is invalid Each time the valid edge is input the values of TM50 and TM60 are incremented When the count values of TM50 and TM60 s...

Page 162: ...lse TM50 00H X 01H CR50 X X X 7FH 80H FFH 00H N 00H N N N X X 1 00H X 1 Not cleared because TM50 does not match Cleared because TM50 and TM60 match simultaneously Count start Interrupt not generated because TM50 does not match Interrupt acknowledgement Interrupt acknowledgement Remark X 00H to FFH N 00H to FFH Figure 7 17 Timing of External Event Counter Operation with 16 Bit Resolution ...

Page 163: ... TM60 simultaneously match the values set in CR50 and CR60 respectively the TO60 pin output will be inverted Through application of this mechanism square waves of any frequency can be output As soon as a match occurs TM50 and TM60 are cleared to 00H and counting continues At the same time an interrupt request signal INTTM60 is generated INTTM50 is not generated The square wave output is cleared to...

Page 164: ...R50 X X X 7FH 80H FFH 00H N 00H N N N X X 1 00H Not cleared because TM50 does not match Cleared because TM50 and TM60 match simultaneously Count start Interrupt not generated because TM50 does not match Interrupt acknowledgement Interrupt acknowledgement Figure 7 18 Timing of Square Wave Output with 16 Bit Resolution Note The initial value of TO60 or TO61 is low level when output is enabled Remark...

Page 165: ...ed Set P32 to the output mode PM32 0 set the P32 output latch to 0 and set TOE60 to output enable TOE60 1 If TO61 is selected Set P33 to the output mode PM33 0 set the P33 output latch to 0 and set TOE61 to output enable TOE60 1 8 Enable the operation of TM50 and TM60 TCE50 1 TCE60 1 The operation of the carrier generator is as follows 1 When the count value of TM60 matches the value set in CR60 a...

Page 166: ...on instruction must not be used Be sure to use an 8 bit memory manipulation instruction 4 While INTTM50 interrupt generated by the match signal of timer 50 is being output accessing TCA60 is prohibited 5 Accessing TCA60 is prohibited while 8 bit timer counter 50 TM50 is 00H To access TCA60 while TM50 00H wait for more than half a period of the TM50 count clock and then rewrite TCA60 6 To enable op...

Page 167: ...n When CR60 N CRH60 M M N Count clock TM60 count value CR60 TCE60 INTTM60 M 00H N 00H 01H N CRH60 M N 00H Carrier clock N 00H 00H N M 00H 01H L L 00H 01H L 00H 01H L 00H L 00H 01H TM50 CR50 TCE50 INTTM50 Count pulse 0 1 0 1 0 0 1 0 1 0 NRZB60 NRZ60 TO60 or TO61 Carrier clock Clear Clear Clear Clear Count start ...

Page 168: ...ion When CR60 N CRH60 M M N Count clock TM60 count value CR60 TCE60 INTTM60 N 00H N L CRH60 M Carrier clock N 00H 00H 01H L 00H 01H L 00H 01H L 00H L 00H 01H TM50 CR50 TCE50 INTTM50 Count pulse 0 1 0 1 0 0 1 0 1 0 NRZB60 NRZ60 TO60 or TO61 Carrier clock M 00H M M 00H M 00H Clear Clear Clear Clear Count start ...

Page 169: ...on When CR60 CRH60 N Count clock TM60 count value CR60 TCE60 INTTM60 N 00H 00H 00H N CRH60 N N Carrier clock 00H 00H N N 00H 01H L 00H 01H L 00H 01H L 00H L 00H 01H TM50 CR50 TCE50 INTTM50 Count pulse 0 1 0 1 0 0 1 0 1 0 NRZB60 NRZ60 TO60 or TO61 Carrier clock N N 00H Clear Clear Clear Clear Clear Count start ...

Page 170: ...he operation mode of timer 50 to the PWM free running mode see Figure 7 4 5 Set the count clock for timer 50 6 Set P31 to the output mode PM31 0 and the P31 output latch to 0 and enable timer output of TO50 TOE50 1 7 Enable the operation of TM50 TCE50 1 The operation in the PWM free running mode is as follows 1 When the count value of TM50 matches the value set in CR50 an interrupt request signal ...

Page 171: ...Overflow Overflow Count start Caution When the rising edge is selected do not set the CR50 to 00H If the CR50 is set to 00H PWM output may not be performed normally Figure 7 23 Operation Timing When Overwriting CR50 When Rising Edge Is Selected 1 2 1 When setting CR50 TM50 after overflow Count clock CR50 TCE50 INTTM50 TO50 N TM50 N 00H 00H 00H 01H FFH M FFH 01H M Overflow Overflow Overflow Count s...

Page 172: ...50 TO50 N TM50 N 00H 00H 00H 01H FFH FFH 01H 01H 02H 01H Overflow Overflow Overflow Count start CR50 overwrite Overflow occurs but no change takes place because TO50 is high level Figure 7 24 Operation Timing in PWM Free Running Mode When Both Edges Are Selected 1 2 1 CR50 Even number Count clock CR50 TCE50 INTTM50 TO50 2N TM50 2N 00H 00H 01H FFH FFH 2N 02H FEH 01H 02H FEH Overflow Overflow Overfl...

Page 173: ...01H 00H Overflow Overflow Overflow Count start Caution When both edges are selected do not set CR50 to 00H 01H and FFH If the CR50 is set to these values PWM output may not be performed normally Figure 7 25 Operation Timing in PWM Free Running Mode When Both Edges Are Selected When CR50 Is Overwritten Count clock CR50 TCE50 INTTM50 TO50 2N 1 TM50 2N 00H 00H 00H 01H FFH FFH 01H 2N 1 01H 02H FEH 2N ...

Page 174: ...put of TO60 TOE60 1 7 Enable the operation of TM60 TCE60 1 The operation in the PWM output mode is as follows 1 When the count value of TM60 matches the value set in CR60 an interrupt request signal INTTM60 is generated and output of timer 60 is inverted which makes the compare register switch from CR60 to CRH60 2 A match between TM60 and CR60 clears the TM60 value to 00H and then counting starts ...

Page 175: ...M 01H 01H M 00H Clear Clear Clear Clear Count start Note The initial value of TO60 is low level when output is enabled TOE60 1 Figure 7 27 PWM Output Mode Timing When CR60 and CRH60 Are Overwritten Count clock TM60 count value CR60 TCE60 INTTM60 00H N 00H 01H N CRH60 M N TO60 or TO61Note M X Y 00H 00H X 00H X Y M Clear Clear Clear Clear Count start Note The initial value of TO60 is low level when ...

Page 176: ...ed asynchronously to the count pulse Figure 7 28 Start Timing of 8 Bit Timer Counter Count pulse TMn0 count value 00H 01H 02H 03H 04H Timer start Remark n 5 6 2 Setting of 8 bit compare register n0 8 bit compare register n0 CRn0 can be set to 00H Therefore one pulse can be counted when the 8 bit timer operates as an event counter Remark n 5 6 Figure 7 29 Timing of Operation as External Event Count...

Page 177: ... The watch and interval timers can be used at the same time Figure 8 1 is a block diagram of the watch timer Figure 8 1 Block Diagram of Watch Timer fX 27 fXT fW fW 24 fW 25 fW 26 fW 27 fW 28 fW 29 Clear 9 bit prescaler Selector Clear 5 bit counter INTWT INTWTI WTM7 WTM6 WTM5 WTM4 WTM1 WTM0 Watch timer mode control register WTM Internal bus Selector ...

Page 178: ...ied intervals Table 8 1 Interval Generated Using the Interval Timer Interval At fX 5 0 MHz At fX 4 19 MHz At fXT 32 768 kHz 2 4 1 fW 409 6 µs 489 µs 488 µs 2 5 1 fW 819 2 µs 978 µs 977 µs 2 6 1 fW 1 64 ms 1 96 ms 1 95 ms 2 7 1 fW 3 28 ms 3 91 ms 3 91 ms 2 8 1 fW 6 55 ms 7 82 ms 7 81 ms 2 9 1 fW 13 1 ms 15 6 ms 15 6 ms Remarks 1 fW Watch timer clock frequency fX 2 7 or fXT 2 fX Main system clock os...

Page 179: ...er count clock selection WTM7 Prescaler interval selection WTM6 0 0 0 0 1 1 24 fW 488 s 25 fW 977 s 26 fW 1 95 ms 27 fW 3 91 ms 28 fW 7 81 ms 29 fW 15 6 ms WTM5 0 0 1 1 0 0 WTM4 0 1 0 1 0 1 Control of 5 bit counter operation WTM1 0 1 Cleared after stop Started Watch timer operation WTM0 0 1 Operation disabled both prescaler and timer cleared Operation enabled Other than above fX 27 fXT 39 1 kHz 32...

Page 180: ...to 29 1 fW seconds may occur in the overflow INTWT after the zero second start of the watch timer because the 9 bit prescaler is not cleared to 0 8 4 2 Operation as interval timer The interval timer is used to repeatedly generate an interrupt request at the interval specified by a preset count value The interval can be selected by bits 4 to 6 WTM4 to WTM6 of the watch timer mode control register W...

Page 181: ...nd 5 bit counter operation is enabled by setting bit 0 WTM0 of the watch mode timer mode control register WTM to 1 the interval until the first interrupt request INTWT is generated after the register is set does not exactly match the watch timer interrupt time 0 5 s This is because there is a delay of one 9 bit prescaler output cycle until the 5 bit counter starts counting Subsequently however the...

Page 182: ...ay When a runaway is detected a non maskable interrupt or the RESET signal can be generated Table 9 1 Watchdog Timer Runaway Detection Time Runaway Detection Time At fX 5 0 MHz 2 11 1 fX 410 µs 2 13 1 fX 1 64 ms 2 15 1 fX 6 55 ms 2 17 1 fX 26 2 ms fX Main system clock oscillation frequency 2 Interval timer The interval timer generates an interrupt at an arbitrary preset interval Table 9 2 Interval...

Page 183: ...Watchdog timer clock select register WDCS Watchdog timer mode register WDTM Figure 9 1 Block Diagram of Watchdog Timer Internal bus Internal bus Prescaler Selector Controller fX 26 fX 28 fX 210 3 7 bit counter WDTIF WDTMK TCL22 TCL21 TCL20 Watchdog timer clock select register WDCS Watchdog timer mode register WDTM Clear WDTM4 RUN WDTM3 INTWDT Maskable interrupt request RESET INTWDT Non maskable in...

Page 184: ...anipulation instruction RESET input sets WDCS to 00H Figure 9 2 Format of Watchdog Timer Clock Select Register WDCS2 0 0 1 1 WDCS1 0 1 0 1 fX 24 fX 26 fX 28 fX 210 312 5 kHz 78 1 kHz 19 5 kHz 4 88 kHz WDCS0 0 0 0 0 Setting prohibited Other than above Watchdog timer count clock selection 211 fX 213 fX 215 fX 217 fX 410 s 1 64 ms 6 55 ms 26 2 ms Interval µ 0 0 0 0 0 WDCS2 WDCS1 WDCS0 WDCS 7 6 5 4 Sy...

Page 185: ...e 2 Starts reset operation upon overflow occurrence 0 0 RUN 0 0 WDTM4 WDTM3 0 0 0 WDTM 7 6 5 4 Symbol Address After reset R W FFF9H 00H R W 3 2 1 0 Notes 1 Once RUN has been set 1 it cannot be cleared 0 by software Therefore when counting is started it cannot be stopped by any means other than RESET input 2 Once WDTM3 and WDTM4 have been set 1 they cannot be cleared 0 by software 3 The watchdog ti...

Page 186: ...nd the runaway detection time is exceeded a system reset signal or a non maskable interrupt is generated depending on the value of bit 3 WDTM3 of WDTM The watchdog timer continues operation in HALT mode but stops in STOP mode Therefore first set RUN to 1 to clear the watchdog timer before executing the STOP instruction Cautions 1 The actual runaway detection time may be up to 0 8 shorter than the ...

Page 187: ...upt mask flag WDTMK is valid and a maskable interrupt INTWDT can be generated The priority of INTWDT is set as the highest of all the maskable interrupts The interval timer continues operation in HALT mode but stops in STOP mode Therefore first set RUN to 1 to clear the interval timer before executing the STOP instruction Cautions 1 Once bit 4 WDTM4 of WDTM is set to 1 when watchdog timer mode is ...

Page 188: ...og inputs ANI0 to ANI5 is selected for A D conversion A D conversion is performed repeatedly with an interrupt request INTAD0 being issued each time A D conversion is complete 10 2 8 Bit A D Converter Configuration The 8 bit A D converter includes the following hardware Table 10 1 Configuration of 8 Bit A D Converter Item Configuration Analog inputs 6 channels ANI0 to ANI5 Registers Successive app...

Page 189: ...a voltage tap comparison voltage received from the series resistor string starting from the most significant bit MSB Upon receiving all the bits down to the least significant bit LSB that is upon the completion of A D conversion the SAR sends its contents to A D conversion result register 0 ADCR0 2 A D conversion result register 0 ADCR0 ADCR0 holds the result of A D conversion Each time A D conver...

Page 190: ...version Caution Do not supply pins ANI0 to ANI5 with voltages that fall outside the rated range If a voltage greater than AVDD or less than AVSS even if within the absolute maximum rating is applied to any of these pins the conversion value for the corresponding channel will be undefined Furthermore the conversion values for the other channels may also be affected 7 AVSS pin The AVSS pin is a grou...

Page 191: ... FR02 0 0 0 1 1 1 144 fX 120 fX 96 fX 72 fX 60 fX 48 fX FR01 0 0 1 0 0 1 28 8 s 24 s 19 2 s 14 4 s Setting prohibitedNote 2 Setting prohibitedNote 2 µ µ µ FR00 0 1 0 0 1 0 Other than above Conversion disabled Conversion enabled Setting prohibited µ ADCS0 0 FR02 FR01 FR00 0 0 0 ADM0 7 6 5 4 Symbol Address After reset R W FF80H 00H R W 3 2 1 0 Notes 1 The specifications of FR02 FR01 and FR00 must be...

Page 192: ...0 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets ADS0 to 00H Figure 10 3 Format of Analog Input Channel Specification Register 0 0 0 0 0 0 ADS02 ADS01 ADS00 ADS0 Symbol Address After reset R W FF84H 00H R W 7 6 5 4 3 2 1 0 Analog input channel specification Other than above ADS02 0 0 0 0 1 1 ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 Setting prohibited ADS01 0 0 1 1 0 0 ADS00 0 1...

Page 193: ...f AVDD the MSB of SAR is left set If it is lower than half of AVDD the MSB is reset 6 Bit 6 of SAR is set automatically and comparison shifts to the next stage The next tap voltage of the series resistor string is selected according to bit 7 which reflects the previous comparison result as follows Bit 7 1 Three quarters of AVDD Bit 7 0 One quarter of AVDD The tap voltage is compared with the analo...

Page 194: ...ersion is canceled In this case A D conversion is restarted from the beginning if ADCS0 is set 1 RESET input makes A D conversion result register 0 ADCR0 undefined 10 4 2 Input voltage and conversion result The relationships between the analog input voltage at the analog input pins ANI0 to ANI5 and the A D conversion result A D conversion result register 0 ADCR0 are represented by ADCR0 INT 256 0 ...

Page 195: ...IES User s Manual U15075EJ2V1UD 195 Figure 10 5 Relationship Between Analog Input Voltage and A D Conversion Result 255 254 253 3 2 1 0 A D conversion result ADCR0 1 512 1 256 3 512 2 256 5 512 3 256 507 512 254 256 509 512 255 256 511 512 1 Input voltage AVDD ...

Page 196: ...ified in analog input channel specification register 0 ADS0 Upon completion of A D conversion the conversion result is saved to A D conversion result register 0 ADCR0 At the same time an interrupt request signal INTAD0 is generated Once A D conversion is activated and completed another session of A D conversion is started A D conversion is repeated until new data is written to ADM0 If data where A...

Page 197: ...nto a conversion channel the conversion output of the channel becomes undefined which may affect the conversion output of the other channels 3 Conflict 1 Conflict between writing to A D conversion result register 0 ADCR0 at the end of conversion and reading from ADCR0 using instruction Reading from ADCR0 takes precedence After reading the new conversion result is written to ADCR0 2 Conflict betwee...

Page 198: ... operation has been stopped stop the A D conversion operation before the next conversion operation is completed Figures 10 8 and 10 9 show the timing at which the conversion result is read Figure 10 8 Conversion Result Read Timing If Conversion Result Is Undefined End of A D conversion End of A D conversion Normal conversion result Undefined value Normal conversion result is read A D conversion st...

Page 199: ...ion do not execute input instructions for the ports otherwise the conversion resolution may be reduced If a digital pulse is applied to a pin adjacent to the analog input pins during A D conversion coupling noise may occur that prevents an A D conversion result from being obtained as expected Avoid applying a digital pulse to pins adjacent to the analog input pins during A D conversion 8 Interrupt...

Page 200: ... to the analog circuit It is also used to supply power to the ANI0 to ANI5 input circuit If your application is designed to be changed to backup power the AVDD pin must be supplied with the same voltage level as the VDD pin as shown in Figure 10 12 Figure 10 12 AVDD Pin Handling Main power source Backup capacitor VDD AVDD VSS AVSS 10 AVDD pin input impedance A series resistor string of several ten...

Page 201: ...og inputs ANI0 to ANI5 is selected for A D conversion A D conversion is performed repeatedly with an interrupt request INTAD0 being issued each time A D conversion is complete 11 2 10 Bit A D Converter Configuration The 10 bit A D converter includes the following hardware Table 11 1 Configuration of 10 Bit A D Converter Item Configuration Analog inputs 6 channels ANI0 to ANI5 Registers Successive ...

Page 202: ...ends its contents to A D conversion result register 0 ADCR0 2 A D conversion result register 0 ADCR0 ADCR0 is a 16 bit register that holds the result of A D conversion The lower 6 bits are fixed to 0 Each time A D conversion ends the conversion result in the successive approximation register is loaded into ADCR0 The higher 8 bits of the conversion result are loaded into FF15H of ADCR0 and the lowe...

Page 203: ...e the 6 channel analog input pins for the A D converter They are used to receive the analog signals for A D conversion Caution Do not supply pins ANI0 to ANI5 with voltages that fall outside the rated range If a voltage greater than AVDD or less than AVSS even if within the absolute maximum rating is applied to any of these pins the conversion value for the corresponding channel will be undefined ...

Page 204: ...1 FR02 0 0 0 1 1 1 144 fX 120 fX 96 fX 72 fX 60 fX 48 fX FR01 0 0 1 0 0 1 28 8 s 24 s 19 2 s 14 4 s Setting prohibitedNote 2 Setting prohibitedNote 2 µ µ µ FR00 0 1 0 0 1 0 Other than above Conversion disabled Conversion enabled Setting prohibited µ ADCS0 0 FR02 FR01 FR00 0 0 0 ADM0 7 6 5 4 Symbol Address After reset R W FF80H 00H R W 3 2 1 0 Notes 1 The specifications of FR02 FR01 and FR00 must b...

Page 205: ... is set with a 1 bit or 8 bit memory manipulation instruction RESET input clears ADS0 to 00H Figure 11 3 Format of Analog Input Channel Specification Register 0 0 0 0 0 0 ADS02 ADS01 ADS00 ADS0 Symbol Address After reset R W FF84H 00H R W 7 6 5 4 3 2 1 0 Analog input channel specification Other than above ADS02 0 0 0 0 1 1 ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 Setting prohibited ADS01 0 0 1 1 0 0 ADS00 0 ...

Page 206: ...of AVDD the MSB of SAR is left set If it is lower than half of AVDD the MSB is reset 6 Bit 8 of SAR is set automatically and comparison shifts to the next stage The next tap voltage of the series resistor string is selected according to bit 9 which reflects the previous comparison result as follows Bit 9 1 Three quarters of AVDD Bit 9 0 One quarter of AVDD The tap voltage is compared with the anal...

Page 207: ...canceled In this case A D conversion is restarted from the beginning if ADCS0 is set 1 RESET input makes A D conversion result register 0 ADCR0 undefined 11 4 2 Input voltage and conversion result The relationships between the analog input voltage at the analog input pins ANI0 to ANI5 and the A D conversion result A D conversion result register 0 ADCR0 are represented by ADCR0 INT 1 024 0 5 or ADC...

Page 208: ...s Manual U15075EJ2V1UD 208 Figure 11 5 Relationship Between Analog Input Voltage and A D Conversion Result 1023 1022 1021 3 2 1 0 A D conversion result ADCR0 1 2048 1 1024 3 2048 2 1024 5 2048 3 1024 2043 2048 1022 1024 2045 2048 1023 1024 2047 2048 1 Input voltage AVDD ...

Page 209: ...in specified in A D input selection register 0 ADS0 Upon completion of A D conversion the conversion result is saved to A D conversion result register 0 ADCR0 At the same time an interrupt request signal INTAD0 is generated Once A D conversion is activated and completed another session of A D conversion is started A D conversion is repeated until new data is written to ADM0 If data where ADCS0 is ...

Page 210: ...into a conversion channel the conversion output of the channel becomes undefined which may affect the conversion output of the other channels 3 Conflict 1 Conflict between writing to A D conversion result register 0 ADCR0 at the end of conversion and reading from ADCR0 using instruction Reading from ADCR0 takes precedence After reading the new conversion result is written to ADCR0 2 Conflict betwe...

Page 211: ...n operation has been stopped stop the A D conversion operation before the next conversion operation is completed Figures 11 8 and 11 9 show the timing at which the conversion result is read Figure 11 8 Conversion Result Read Timing If Conversion Result Is Undefined End of A D conversion End of A D conversion Normal conversion result Undefined value Normal conversion result is read A D conversion s...

Page 212: ...sion do not execute input instructions for the ports otherwise the conversion resolution may be reduced If a digital pulse is applied to a pin adjacent to the analog input pins during A D conversion coupling noise may occur that prevents an A D conversion result from being obtained as expected Avoid applying a digital pulse to pins adjacent to the analog input pins during A D conversion 8 Interrup...

Page 213: ...r to the analog circuit It is also used to supply power to the ANI0 to ANI5 input circuit If your application is designed to be changed to backup power the AVDD pin must be supplied with the same voltage level as the VDD pin as shown in Figure 11 12 Figure 11 12 AVDD Pin Handling Main power supply Backup capacitor VDD AVDD VSS AVSS 10 AVDD pin input impedance A series resistor string of several te...

Page 214: ... As it supports simultaneous transmission and reception 3 wire serial I O mode requires less processing time for data transmission than asynchronous serial interface mode Because in 3 wire serial I O mode it is possible to select whether 8 bit data transmission begins with the MSB or LSB serial interface 20 can be connected to any device regardless of whether that device is designed for MSB first ...

Page 215: ...hift clock SI20 P25 RxD20 SO20 P24 TxD20 4 Parity detection Stop bit detection Reception data counter Parity operation Stop bit addition Transmission data counter SL20 CL20 PS200 PS201 Reception enabled Reception clock Detection clock Start bit detection CSIE20 CSCK20 SCK20 P23 ASCK20 SS20 P22 Clock phase control Reception detected Internal clock output External clock input Transmission and recept...

Page 216: ...Reception buffer register 20 RXB20 RXB20 holds a reception data A new reception data is transferred from reception shift register 20 RXS20 every 1 byte data reception When the data length is seven bits the reception data is sent to bits 0 to 6 of RXB20 in which the MSB is always fixed to 0 RXB20 can be read with an 8 bit memory manipulation instruction but cannot be written RESET input makes RXB20...

Page 217: ...on control CSIE20 SSE20 0 0 DAP20 DIR20 CSCK20 CKP20 CSIM20 Symbol Address After reset R W FF72H 00H R W 7 6 5 4 3 2 1 0 Operation disabled Operation enabled DIR20 0 1 First bit specification MSB LSB CSCK20 0 1 3 wire serial I O mode clock selection External clock input to the SCK20 pin Output of the dedicated baud rate generator SSE20 0 1 Not used Used DAP20 0 1 3 wire serial I O mode data phase ...

Page 218: ... reset R W FF70H 00H R W 7 6 5 4 3 2 1 0 Transmit operation stop Transmit operation enable RXE20 0 1 Receive operation control Receive operation stop Receive operation enable PS201 0 0 1 1 Parity bit specification PS200 0 1 0 1 No parity Always add 0 parity at transmission Parity check is not performed at reception No parity error is generated Odd parity Even parity CL20 0 1 Transmit data characte...

Page 219: ...ock SCK20 output 0 1 External clock SCK20 input 0 0 1 1 1 Note 2 Note 2 0 1 0 1 LSB Internal clock SI20Note 2 SO20 CMOS output SCK20 output Other than above Setting prohibited 3 Asynchronous serial interface mode ASIM20 CSIM20 TXE20 RXE20 CSIE20 DIR20 CSCK20 PM25 P25 PM24 P24 PM23 P23 First Bit Shift Clock P25 SI20 RxD20 Pin Function P24 SO20 TxD20 Pin Function P23 SCK20 ASCK20 Pin Function 1 Exte...

Page 220: ... No parity error has occurred A parity error has occurred when the transmit parity and receive parity did not match FE20 0 1 Flaming error flag No framing error has occurred A framing error has occurred when stop bit is not detected Note 1 OVE20 0 1 Overrun error flag No overrun error has occurred An overrun error has occurred Note 2 when the next receive operation is completed before the data is ...

Page 221: ...rohibited 2 5 MHz 1 25 MHz 625 kHz 313 kHz 156 kHz 78 1 kHz 39 1 kHz 19 5 kHz Other than above TPS201 0 0 1 1 0 0 1 1 0 TPS200 0 1 0 1 0 1 0 1 0 n 1 2 3 4 5 6 7 8 Note An external clock can be used only in UART mode Cautions 1 When writing to BRGC00 during a communication operation the output of the baud rate generator is disrupted and communications cannot be performed normally Be sure not to wri...

Page 222: ...te of a clock generated from the system clock is estimated by using the following expression Baud rate bps fX Main system clock oscillation frequency n Value determined by the settings of TPS200 to TPS203 as shown in Figure 12 6 2 n 8 Table 12 3 Example of Relationships Between System Clock and Baud Rate Error Baud Rate bps n BRGC20 Set Value fX 5 0 MHz fX 4 9152 MHz 1 200 8 70H 2 400 7 60H 4 800 ...

Page 223: ...n Input Frequency and Baud Rate When BRGC20 Is Set to 80H Baud Rate bps ASCK20 Pin Input Frequency kHz 75 1 2 150 2 4 300 4 8 600 9 6 1 200 19 2 2 400 38 4 4 800 76 8 9 600 153 6 19 200 307 2 31 250 500 0 38 400 614 4 c Generation of serial clock in 3 wire serial I O mode from system clock The serial clock is generated by dividing the system clock The serial clock frequency is estimated by using t...

Page 224: ...D20 and P25 SI20 RxD20 pins can be used as normal I O ports 1 Register setting Operation stop mode is set by serial operation mode register 20 CSIM20 and asynchronous serial interface mode register 20 ASIM20 a Serial operation mode register 20 CSIM20 CSIM20 is set with a 1 bit or 8 bit memory manipulation instruction RESET input clears CSIM20 to 00H CSIE20 0 1 Operation control in 3 wire serial I ...

Page 225: ...ation instruction RESET input sets ASIM20 to 00H TXE20 0 1 Transmit operation control Transmit operation stopped Transmit operation enabled Receive operation stopped Receive operation enabled RXE20 0 1 Receive operation control TXE20 RXE20 PS201 PS200 CL20 SL20 0 0 ASIM20 7 6 5 4 Symbol Address After reset R W FF70H 00H R W 3 2 1 0 Caution Bits 0 and 1 must be set to 0 ...

Page 226: ...s at the desired baud rate In addition the baud rate can also be defined by dividing the clock input to the ASCK20 pin The UART dedicated baud rate generator also can output the 31 25 kbps baud rate that complies with the MIDI standard 1 Register setting UART mode is set by serial operation mode register 20 CSIM20 asynchronous serial interface mode register 20 ASIM20 asynchronous serial interface ...

Page 227: ...specification MSB LSB CSCK20 0 1 3 wire serial I O mode clock selection External clock input to the SCK20 pin Output of the dedicated baud rate generator SSE20 0 1 Not used Used DAP20 0 1 3 wire serial I O mode data phase selection Outputs at the falling edge of SCK20 Outputs at the rising edge of SCK20 SS20 pin selection Function of SS20 P22 pin Port function 0 1 Communication status Communicatio...

Page 228: ... 0 1 0 1 0 0 0 1 0 1 1 1 No parity Always add 0 parity at transmission Parity check is not performed at reception No parity error is generated Odd parity Even parity Receive operation control PS201 Parity bit specification PS200 CL20 0 1 SL20 Character length specification 7 bits 8 bits 1 bit 2 bits Transmit data stop bit length specification TXE20 RXE20 PS201 PS200 CL20 SL20 0 0 ASIM20 7 6 5 4 Sy...

Page 229: ...1 No overrun error has occurred An overrun error has occurredNote 2 when the next receive operation is completed before data is read from reception buffer register 20 FE20 0 1 0 1 Framing error flag Overrun error flag OVE20 0 0 0 0 0 PE20 FE20 OVE20 ASIS20 7 6 5 4 Symbol Address After reset R W FF71H 00H R 3 2 1 0 Notes 1 Even when the stop bit length is set to 2 bits by setting bit 2 SL20 of asyn...

Page 230: ...above TPS203 TPS202 TPS201 TPS200 0 0 0 0 BRGC20 7 6 5 4 Symbol Address After reset R W FF73H 00H R W 3 2 1 0 Note Can only be used in the UART mode Cautions 1 When writing to BRGC20 during a communication operation the output of the baud rate generator is disrupted and communications cannot be performed normally Be sure not to write to BRGC20 during a communication operation 2 Be sure not to sele...

Page 231: ...lock generated from the system clock is estimated by using the following expression Baud rate bps fX Main system clock oscillation frequency n Values determined by the settings of TPS200 to TPS203 as shown in the above table 2 n 8 Table 12 5 Example of Relationships Between System Clock and Baud Rate Error Baud Rate bps n BRGC20 Set Value fX 5 0 MHz fX 4 9152 MHz 1 200 8 70H 2 400 7 60H 4 800 6 50...

Page 232: ...The baud rate of a clock generated from the clock input to the ASCK20 pin is estimated by using the following expression Baud rate bps fASCK Frequency of clock input to ASCK20 pin Table 12 6 Relationship Between ASCK20 Pin Input Frequency and Baud Rate When BRGC20 Is Set to 80H Baud Rate bps ASCK20 Pin Input Frequency kHz 75 1 2 150 2 4 300 4 8 600 9 6 1 200 19 2 2 400 38 4 4 800 76 8 9 600 153 6 ...

Page 233: ... Transmit Receive Data D0 D1 D2 D3 D4 D5 D6 D7 Parity bit Stop bit Start bit One data frame Start bits 1 bit Character bits 7 bits 8 bits Parity bits Even parity odd parity 0 parity no parity Stop bits 1 bit 2 bits When 7 bits are selected as the number of character bits only the lower 7 bits bits 0 to 6 are valid in transmission the most significant bit bit 7 is ignored and in reception the most ...

Page 234: ... parity bit is counted and if the number is odd a parity error occurs ii Odd parity At transmission Conversely to the even parity the parity bit is determined so that the number of bits with a value of 1 in the transmit data including parity bit may be odd The parity bit value should be as follows The number of bits with a value of 1 is an odd number in transmit data 0 The number of bits with a va...

Page 235: ... Transmission Completion Interrupt Timing a Stop bit length 1 STOP Parity D7 D6 D2 D1 D0 START TxD20 output INTST20 b Stop bit length 2 STOP Parity D7 D6 D2 D1 D0 START TxD20 output INTST20 Caution Do not rewrite asynchronous serial interface mode register 20 ASIM20 during a transmit operation If the ASIM20 register is rewritten during transmission subsequent transmission may not be able to be per...

Page 236: ...cted after the start bit reception of one frame of data ends When one frame of data has been received the receive data in the shift register is transferred to reception buffer register 20 RXB20 and a reception completion interrupt INTSR20 is generated If an error occurs the receive data in which the error occurred is still transferred to RXB20 and INTSR20 is generated If the RXE20 bit is reset 0 d...

Page 237: ...et Table 12 7 Receive Error Causes Receive Errors Cause Parity error Transmission time parity and reception data parity do not match Framing error Stop bit not detected Overrun error Reception of next data is completed before data is read from reception buffer register Figure 12 10 Receive Error Timing a Parity error occurrence STOP Parity D7 D6 D2 D1 D0 START RxD20 input INTSR20 b Framing error o...

Page 238: ...bit 6 RXE20 of asynchronous serial interface mode register 20 ASIM20 is cleared during reception reception buffer register 20 RXB20 and the receive completion interrupt INTSR20 are as follows Parity RxD20 pin RXB20 INTSR20 3 1 2 When RXE20 is set to 0 at a time indicated by 1 RXB20 holds the previous data and INTSR20 is not generated When RXE20 is set to 0 at a time indicated by 2 RXB20 renews the...

Page 239: ...cked serial interface such as the 75XL Series 78K Series and 17K Series Communication is performed using three lines a serial clock SCK20 serial output SO20 and serial input SI20 1 Register setting 3 wire serial I O mode settings are performed using serial operation mode register 20 CSIM20 asynchronous serial interface mode register 20 ASIM20 baud rate generator control register 20 BRGC20 port mod...

Page 240: ...xternal clock input to the SCK20 pinNote Output of the dedicated baud rate generator SSE20 0 1 Not used Used DAP20 0 1 3 wire serial I O mode data phase selection Outputs at the falling edge of SCK20 Outputs at the rising edge of SCK20 SS20 pin selection Function of SS20 P22 pin Port function 0 1 Communication status Communication enabled Communication enabled Communication disabled CKP20 0 1 3 wi...

Page 241: ...ceive operation enabled RXE20 0 1 0 1 0 0 0 1 0 1 1 1 No parity Always add 0 parity at transmission Parity check is not performed at reception No parity error occurs Odd parity Even parity Receive operation control PS201 Parity bit specification PS200 CL20 0 1 SL20 Transmit data character length specification 7 bits 8 bits 1 bit 2 bits Transmit data stop bit length specification TXE20 RXE20 PS201 ...

Page 242: ... When writing to BRGC20 during a communication operation the baud rate generator output is disrupted and communications cannot be performed normally Be sure not to write to BRGC20 during a communication operation Remarks 1 fX Main system clock oscillation frequency 2 n Values determined by the settings of TPS200 to TPS203 1 n 8 3 The parenthesized values apply to operation at fX 5 0 MHz If the int...

Page 243: ...Then transmit data is held in the SO20 latch and output from the SO20 pin Also receive data input to the SI20 pin is latched in the reception buffer register RXB20 SIO20 on the rise of SCK20 At the end of an 8 bit transfer the operation of TXS20 SIO20 and RXS20 stops automatically and the interrupt request signal INTCSI20 is generated Figure 12 11 3 Wire Serial I O Mode Timing 1 7 i Master operati...

Page 244: ...O0 SCK20 SI20 Note SO20 SIO20 write INTCSI20 Note The value of the last bit previously output is output iii Slave operation when DAP20 0 CKP20 0 SSE20 1 1 2 3 4 5 6 7 8 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DO7 Note 1 DO6 DO5 DO4 DO3 DO2 DO1 DO0Note 2 SCK20 SI20 SO20 Hi Z Hi Z SS20 SIO20 write INTCSI20 Notes 1 The value of the last bit previously output is output 2 DO0 is output until SS20 rises When SS...

Page 245: ...O0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 SCK20 SO20 SI20 SIO20 write INTCSI20 v Slave operation when DAP20 0 CKP20 1 SSE20 0 1 2 3 4 5 6 7 8 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 SCK20 SI20 SO20 SIO20 write INTCSI20 SIO20 write master Note Note The data of SI20 is loaded at the first rising edge of SCK20 Make sure that the master outputs the first bit before the first rising of...

Page 246: ...te SS20 INTCSI20 DO0 SIO20 write master Note 1 Notes 1 The data of SI20 is loaded at the first rising edge of SCK20 Make sure that the master outputs the first bit before the first rising of SCK20 2 SO20 is high until SS20 rises after completion of DO0 output When SS20 is high SO20 is in a high impedance state vii Master operation when DAP20 1 CKP20 0 SSE20 0 1 2 3 4 5 6 7 8 DO7 DO6 DO5 DO4 DO3 DO...

Page 247: ...K20 Make sure that the master outputs the first bit before the first falling of SCK20 ix Slave operation when DAP20 1 CKP20 0 SSE20 1 1 2 3 4 5 6 7 8 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 Note 2 SCK20 SI20 Hi Z Hi Z SO20 SIO20 write SS20 INTCSI20 DO0 SIO20 write master Note 1 Notes 1 The data of SI20 is loaded at the first falling edge of SCK20 Make sure that the master outpu...

Page 248: ...DO6 DO5 DO4 DO3 DO2 DO1 DI7 DI6 DI5 DI4 DI3 DI2 DI1 SCK20 SO20 SI20 SIO20 write INTCSI20 DI0 DO0 Note The value of the last bit previously output is output xi Slave operation when DAP20 1 CKP20 1 SSE20 0 1 2 3 4 5 6 7 8 DI7 DI6 DI5 DI4 DI3 DI2 DI1 SCK20 SI20 SO20 SIO20 write INTCSI20 DO7 Note DO6 DO5 DO4 DO3 DO2 DO1 DO0 DI0 Note The value of the last bit previously output is output ...

Page 249: ... until SS20 rises When SS20 is high SO20 is in a high impedance state 3 Transfer start Serial transfer is started by setting transfer data to the transmission shift register TXS20 SIO20 when the following two conditions are satisfied Bit 7 CSIE20 of serial operation mode register 20 CSIM20 1 Internal serial clock is stopped or SCK20 is high after 8 bit serial transfer Caution If CSIE20 is set to 1...

Page 250: ...t Outputs and Maximum Number of Pixels Bias Method Time Slots Common Signals Used Maximum Number of Segments Maximum Number of Pixels 3 COM0 to COM2 15 5 segments 3 commons µPD789426 789436 Subseries 4 COM0 to COM3 5 20 5 segments 4 commons 3 COM0 to COM2 45 15 segments 3 commons µPD789446 789456 Subseries 1 3 4 COM0 to COM3 15 60 15 segments 4 commons 13 2 LCD Controller Driver Configuration The ...

Page 251: ...LC1 VAON0 3 2 1 0 3 2 1 0 6 5 7 4 FA05H LCDON0 S5 LCDM00 LCD clock control register 0 LCDC0 LCD display mode register 0 LCDM0 LCD clock selector Clock generator for boosting Selector Prescaler Booster circuit Segment voltage controller Common voltage controller Common driver Segment driver Segment driver Segment driver Segment driver Selector Selector Selector Selector PD789446 789456 Subseries on...

Page 252: ... LCD clock control register 0 LCDC0 LCD voltage amplification control register 0 LCDVA0 1 LCD display mode register 0 LCDM0 LCDM0 specifies whether to enable display operation It also specifies the operation mode LCD drive power supply and display mode LCDM0 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets LCDM0 to 00H ...

Page 253: ... mode 1 3 1 3 Note When the LCD display panel is not used the VAON0 and LIPS0 must be set to 0 to reduce power consumption Cautions 1 Bits 1 to 3 and 5 must be set to 0 2 When operating VAON0 follow the procedure described below A To stop voltage amplification after switching display status from on to off 1 Set to display off status by setting LCDON0 0 2 Disable outputs of all the segment buffers ...

Page 254: ... 29 fXT 32 768 kHz fX 25 156 3 kHz fX 26 78 1 kHz fX 27 39 1 kHz Note Specify an LCD source clock fLCD frequency of at least 32 kHz Cautions 1 Bits 4 to 7 must be set to 0 2 Before changing the LCDC0 setting be sure to stop voltage amplification VAON0 0 3 Set the frame frequency to 128 Hz or lower Remarks 1 fX Main system clock oscillation frequency 2 fXT Subsystem clock oscillation frequency 3 Th...

Page 255: ...Voltage Amplification Control Register 0 0 GAIN LCDVA0 Symbol Address After reset R W FFB3H 00H R W 7 6 5 4 3 2 1 0 GAIN 0 1 1 5 times specification of the LCD panel used is 4 5 V 1 0 times specification of the LCD panel used is 3 V 0 0 0 0 0 0 Reference voltage VLC2 level selectionNote Note Select the settings according to the specifications of the LCD panel that is used Caution Before changing t...

Page 256: ...tential 7 Start output corresponding to each data memory by setting LCDON0 bit 7 of LCDM0 LCDON0 1 13 5 LCD Display Data Memory The LCD display data memory is mapped at addresses FA00H to FA0EH Data in the LCD display data memory can be displayed on the LCD panel using the LCD controller driver Figure 13 5 shows the relationship between the contents of the LCD display data memory and the segment c...

Page 257: ...nals The segment signals correspond to LCD display data memory Bits 0 1 2 and 3 of each byte are read in synchronization with COM0 COM1 COM2 and COM3 respectively If the contents of each bit are 1 it is converted to the select voltage and if 0 it is converted to the deselect voltage The conversion results are output to the segment pins Check with the information given above what combination of the...

Page 258: ...t signals Figure 13 6 Common Signal Waveforms COMn Three time slot mode TF 3 T VLC0 VSS VLCD VLC1 VLC2 TF 4 T COMn Four time slot mode VLC0 VLCD VLC1 VLC2 VSS T One LCD clock period TF Frame frequency Figure 13 7 Voltages and Phases of Common and Segment Signals Select Deselect Common signal Segment signal VLC0 VSS VLCD VLC0 VSS VLCD T T VLC2 VLC2 VLC1 VLC1 T One LCD clock period ...

Page 259: ...essary to apply the select or deselect voltage to the S6 to S8 pins according to Table 13 5 at the timing of the common signals COM0 to COM2 Table 13 5 Select and Deselect Voltages COM0 to COM2 Segment Common S6 S7 S8 COM0 Select Select Deselect COM1 Select Select Deselect COM2 Select Select According to Table 13 6 it is determined that the display data memory location FA06H that corresponds to S6...

Page 260: ... 1 1 0 0 1 0 Bit 0 Bit 1 Bit 2 Bit 3 Timing strobe Data memory address LCD panel FA00H 1 2 3 4 5 6 7 8 9 A B C D E S 0 S 1 S 2 S 3 S 4 S 5 S 6 S 7 S 8 S 9 S 10 S 11 S 12 S 13 S 14 COM 3 COM 2 COM 1 COM 0 Open x x x x x x Can be used to store any data because there is no corresponding segment in the LCD panel Can always be used to store any data because of the three time slot mode being used ...

Page 261: ... Figure 13 10 Three Time Slot LCD Drive Waveform Examples VLC0 VLC2 COM0 VLCD 0 COM0 S6 VLCD VLC1 1 3VLCD 1 3VLCD VSS0 VLC0 VLC2 COM1 VLC1 VSS0 VLC0 VLC2 COM2 VLC1 VSS0 VLC0 VLC2 S6 VLC1 VSS0 VLCD 0 COM1 S6 VLCD 1 3VLCD 1 3VLCD VLCD 0 COM2 S6 VLCD 1 3VLCD 1 3VLCD TF ...

Page 262: ...ary to apply the select or deselect voltage to the S2 and S3 pins according to Table 13 6 at the timing of the common signals COM0 to COM3 Table 13 6 Select and Deselect Voltages COM0 to COM3 Segment Common S2 S3 COM0 Select Select COM1 Deselect Select COM2 Select Select COM3 Select Select According to Table 13 7 it is determined that the display data memory location FA02H that corresponds to S2 m...

Page 263: ...ur Time Slot LCD Panel 0 0 0 1 0 1 1 0 1 1 1 1 0 1 0 1 1 1 1 1 1 1 1 0 1 0 0 1 0 1 1 0 0 1 0 1 0 1 1 1 0 1 0 0 1 0 1 0 0 0 1 0 1 1 0 0 Bit 0 Bit 1 Bit 2 Bit 3 Timing strobe Data memory address LCD panel FA00H 1 2 3 4 5 6 7 8 9 A B C D S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 COM 3 COM 2 COM 1 COM 0 ...

Page 264: ...ime Slot LCD Drive Waveform Examples Remark The waveforms of COM2 S2 and COM3 S2 are omitted TF VLC0 VLC2 COM0 VLCD 0 COM0 S2 VLCD VLC1 1 3VLCD 1 3VLCD VSS VLC0 VLC2 COM1 VLC1 VSS VLC0 VLC2 COM2 VLC1 VSS VLC0 VLC2 COM3 VLC1 VSS VLCD 0 COM1 S2 VLCD 1 3VLCD 1 3VLCD VLC0 VLC2 S2 VLC1 VSS ...

Page 265: ...equires an external capacitor recommended value 0 47 µF because it employs a capacitance division method to generate a supply voltage to drive the LCD Table 13 7 Output Voltages of VLC0 to VLC2 Pins LCDVA0 GAIN 0 GAIN 1 LCD Drive Power Supply Pin VLC0 4 5 V 3 0 V VLC1 3 0 V 2 0 V VLC2 LCD reference voltage 1 5 V 1 0 V Cautions 1 When using the LCD function do not leave the VLC0 VLC1 and VLC2 pins ...

Page 266: ...ted One interrupt source from the watchdog timer is incorporated as a non maskable interrupt 2 Maskable interrupt This interrupt undergoes mask control If two or more interrupts with the same priority are simultaneously generated each interrupt has a predetermined priority as shown in Table 14 1 A standby release signal is generated 5 external and 9 internal interrupt sources are incorporated as m...

Page 267: ...of serial interface 20 UART transmission 0012H 7 INTWTI Interval timer interrupt 0014H 8 INTTM90 Generation of match signal of 16 bit timer 90 0016H 9 INTTM50 Generation of match signal of 8 bit timer 50 0018H 10 INTTM60 Generation of match signal of 8 bit timer 60 001AH 11 INTAD0 End of A D conversion signal 001CH 12 INTWT Watch timer interrupt Internal 001EH B Maskable 13 INTKR00 Key return sign...

Page 268: ...ble interrupt MK IF IE Internal bus Interrupt request Vector table address generator Standby release signal C External maskable interrupt MK IF IE Internal bus INTM0 INTM1 KRM00 Interrupt request Edge detector Vector table address generator Standby release signal INTM0 External interrupt mode register 0 INTM1 External interrupt mode register 1 KRM00 Key return mode register 00 IF Interrupt request...

Page 269: ...ey return mode register 00 KRM00 Table 14 2 gives a listing of interrupt request flag and interrupt mask flag names corresponding to interrupt requests Table 14 2 Flags Corresponding to Interrupt Request Signal Name Interrupt Request Signal Name Interrupt Request Flag Interrupt Mask Flag INTWDT INTP0 INTP1 INTP2 INTP3 INTSR20 INTCSI20 INTST20 INTWTI INTTM90 INTTM50 INTTM60 INTAD0 INTWT INTKR00 WDT...

Page 270: ... set to 0 2 The WDTIF flag is R W enabled only when a watchdog timer is used as an interval timer If the watchdog timer mode 1 or 2 is used set the WDTIF flag to 0 3 Because port 3 has an alternate function as the external interrupt input when the output level is changed by specifying the output mode of the port function an interrupt request flag is set Therefore the interrupt mask flag should be ...

Page 271: ... read when the watchdog timer is used in watchdog timer mode 1 or 2 its value becomes undefined 3 Because port 3 has an alternate function as the external interrupt input when the output level is changed by specifying the output mode of the port function an interrupt request flag is set Therefore the interrupt mask flag should be set to 1 before using the output mode 0 1 1 KRMK00 WTMK ADMK0 TMMK60...

Page 272: ...1 1 0 1 0 1 Symbol Address After reset INTP0 valid edge selection Falling edge Rising edge Setting prohibited Both rising and falling edges INTP1 valid edge selection Falling edge Rising edge Setting prohibited Both rising and falling edges INTP2 valid edge selection Falling edge Rising edge Setting prohibited Both rising and falling edges ES00 ES01 ES11 ES10 ES20 ES21 Cautions 1 Bits 0 and 1 must...

Page 273: ...sable interrupts After that clear 0 PIF3 then set PMK3 to 0 to enable interrupts 5 Program status word PSW The program status word is a register used to hold the instruction execution result and the current status for interrupt requests The IE flag to set maskable interrupt enable disable is mapped Besides 8 bit unit read write this register can carry out operations with a bit manipulation instruc...

Page 274: ...f MK1 KRMK00 1 to disable interrupts After setting KRM00 clear KRMK00 after clearing bit 6 of IF1 KRIF00 0 to enable interrupts 3 When P00 to P03 are in input mode on chip pull up resistors are connected to P00 to P03 by the setting of KRM000 After switching to output mode the on chip pull up resistors are cut off However key return signal detection continues 4 If any of the pins specified for key...

Page 275: ...stack in that order the IE flag is reset to 0 the contents of the vector table are loaded to the PC and then program execution branches Figure 14 9 shows the flow from non maskable interrupt request generation to acknowledgement Figure 14 10 shows the timing of non maskable interrupt acknowledgement and Figure 14 11 shows the acknowledgement operation when a number of non maskable interrupts are g...

Page 276: ...enerated Interrupt servicing starts WDTM3 0 non maskable interrupt is selected WDTM Watchdog timer mode register WDT Watchdog timer Figure 14 10 Timing of Non Maskable Interrupt Request Acknowledgment Instruction Instruction Saving PSW and PC and jump to interrupt servicing Interrupt servicing program CPU processing WDTIF Figure 14 11 Non Maskable Interrupt Request Acknowledgment Second interrupt ...

Page 277: ...1 clock fCPU CPU clock When two or more maskable interrupt requests are generated at the same time they are acknowledged starting from the one assigned the highest priority by the priority specification flag A pending interrupt is acknowledged when the status where it can be acknowledged is set Figure 14 12 shows the algorithm of interrupt request acknowledgement When a maskable interrupt request ...

Page 278: ...in Final Clock Under Execution Clock CPU NOP MOV A r Saving PSW and PC and jump to interrupt servicing Interrupt servicing program Interrupt 8 clocks If the interrupt request flag XXIF is generated in the final clock of the instruction interrupt request acknowledgment processing will begin after execution of the next instruction is complete Figure 14 14 shows an example whereby an interrupt reques...

Page 279: ...quest is acknowledged the EI instruction is issued and the interrupt request is enabled Example 2 Multiple interrupts are not performed because interrupts are disabled INTyy EI Main servicing RETI INTyy servicing INTxx servicing IE 0 INTxx RETI INTyy is held pending IE 0 Because interrupt requests are disabled the EI instruction has not been issued in the interrupt INTxx servicing the interrupt re...

Page 280: ...rrupt is generated when a certain type of instruction is being executed the interrupt request will not be acknowledged until the instruction is completed Such instructions interrupt request pending instructions are as follows Instructions that manipulate interrupt request flag registers 0 1 IF0 and IF1 Instructions that manipulate interrupt mask flag registers 0 1 MK0 and MK1 ...

Page 281: ...e entire system The power consumption of the CPU can be substantially reduced in this mode The data memory can be retained at the low voltage VDD 1 8 V Therefore this mode is useful for retaining the contents of the data memory at an extremely low power consumption The STOP mode can be released by an interrupt request so that this mode can be used for intermittent operation However some time is re...

Page 282: ...illation stabilization time is fixed to 27 fCC Figure 15 1 Format of Oscillation Stabilization Time Select Register OSTS2 0 0 1 0 0 0 0 0 OSTS2 OSTS1 OSTS0 OSTS R W FFFAH 04H R W 7 6 5 4 3 2 1 0 OSTS1 0 1 0 212 fX 215 fX 217 fX 819 s 6 55 ms 26 2 ms OSTS0 0 0 0 Setting prohibited Symbol Address After reset Oscillation stabilization time selection Other than above µ Caution The wait time after the ...

Page 283: ... bit timer Operation enabled Operation stopped TM50 Operation enabled Note 1 8 bit timer TM60 Operation enabled Operation enabled Note 2 Watch timer Operation enabled Operation enabled Note 3 Operation enabled Operation enabled Note 4 Watchdog timer Operation enabled Operation stopped Serial interface Operation enabled Operation stopped Note 5 A D converter Operation stopped LCD controller driver ...

Page 284: ...s executed Figure 15 2 Releasing HALT Mode by Interrupt HALT instruction Standby release signal Wait Wait HALT mode Operation mode Operation mode Clock Oscillation Remarks 1 The broken line indicates the case where the interrupt request that has released the standby mode is acknowledged 2 The wait time is as follows When vectored interrupt processing is performed 9 to 10 clocks When vectored inter...

Page 285: ...ion RESET signal Wait 215 fX 6 55 ms Reset period HALT mode Operation mode Oscillation stabilization wait status Clock Operation mode Oscillation stops Oscillation Oscillation Remark fX Main system clock oscillation frequency Table 15 2 Operation After Releasing HALT Mode Releasing Source MKxx IE Operation 0 0 Executes next address instruction 0 1 Executes interrupt servicing Maskable interrupt re...

Page 286: ...ystem Clock Is Running Item While the subsystem clock is running While the subsystem clock is not running Main system clock Oscillation stopped CPU Operation stopped Port output latch Remains in the state existing before the selection of STOP mode 16 bit timer Operation stopped TM50 Operation enabled Note 1 8 bit timer TM60 Operation enabled Note 2 Watch timer Operation enabled Note 3 Operation st...

Page 287: ...red interrupt processing is performed after the oscillation stabilization time has elapsed If the interrupt is disabled the instruction at the next address is executed Figure 15 4 Releasing STOP Mode by Interrupt STOP instruction Standby release signal Wait set time by OSTS STOP mode Operation mode Oscillation stabilization wait status Clock Operation mode Oscillation stops Oscillation Oscillation...

Page 288: ...ut STOP instruction RESET signal Wait STOP mode Operation mode Oscillation stabilization wait status Clock Operation mode Oscillation stops Oscillation Oscillation Reset period Remark fX Main system clock oscillation frequency Table 15 4 Operation After Releasing STOP Mode Releasing Source MKxx IE Operation 0 0 Executes next address instruction 0 1 Executes interrupt servicing Maskable interrupt r...

Page 289: ...r during oscillation stabilization time just after reset clear When a high level is input to the RESET pin the reset is cleared and program execution is started after the oscillation stabilization time has elapsed The reset applied by the watchdog timer overflow is automatically cleared after reset and program execution is started after the oscillation stabilization time has elapsed see Figures 16...

Page 290: ...erflow in Watchdog Timer X1 Overflow in watchdog timer Internal reset signal Port pin Hi Z During normal operation Reset period oscillation continues Normal operation reset processing Oscillation stabilization time wait Figure 16 4 Reset Timing by RESET Input in STOP Mode X1 RESET Internal reset signal Port pin Delay Delay Hi Z STOP instruction execution During normal operation Reset period oscill...

Page 291: ...Capture register TCP90 Undefined 16 bit timer Buzzer output control register BZC90 00H Timer counter TM50 TM60 00H Compare register CR50 CR60 CRH60 Undefined Mode control register TMC50 TMC60 00H 8 bit timer Carrier generator output control register TCA60 00H Watch timer Mode control register WTM 00H Clock select register WDCS 00H Watchdog timer Mode register WDTM 00H Serial operation mode registe...

Page 292: ...tatus After Reset Display mode register LCDM0 00H Clock control register LCDC0 00H LCD controller driver Voltage amplification control register LCDVA0 00H Request flag register IF0 IF1 00H Mask flag register MK0 MK1 FFH External interrupt mode register INTM0 INTM1 00H Interrupt Key return mode register KRM00 00H ...

Page 293: ...r Item µPD78F9436 µPD78F9456 µPD789425 789435 µPD789426 789436 µPD789445 789455 µPD789446 789456 ROM 12 KB 16 KB 12 KB 16 KB 12 KB 16 KB High speed RAM 512 bytes Internal memory LCD display RAM 5 4 bits 15 4 bits 5 4 bits 15 4 bits IC pin Not provided Provided VPP pin Provided Not provided Electrical specifications Refer to CHAPTER 20 ELECTRICAL SPECIFICATIONS Caution There are differences in nois...

Page 294: ...rocontroller is solder mounted on the target system Distinguishing software facilities small quantity varied model production Easy data adjustment when starting mass production 17 1 1 Programming environment The following shows the environment required for µPD78F9436 and 78F9456 flash memory programming When Flashpro III part no FL PR3 PG FP3 or Flashpro IV part no FL PR4 PG FP4 is used as a dedic...

Page 295: ...0 to 76 800 bps Notes 2 4 5 MHz Note 5 4 91 or 5 MHz Note 2 1 0 RxD20 SI20 P25 TxD20 SO20 P24 8 Notes 1 Selection items for TYPE settings on the dedicated flash programmer Flashpro III part no FL PR3 PG FP3 Flashpro IV part no FL PR4 PG FP4 2 The possible setting range differs depending on the voltage For details refer to CHAPTER 20 ELECTRICAL SPECIFICATIONS 3 2 or 4 MHz only for Flashpro III 4 Be...

Page 296: ...8F9456 µ Notes 1 When supplying the system clock from a dedicated flash programmer connect the CLK and X1 pins and cut off the resonator on the board When using the clock oscillated by the on board resonator do not connect the CLK pin 2 When using UART with Flashpro III the clock of the resonator connected to the X1 pin must be used so do not connect the CLK pin Caution The VDD pin if already conn...

Page 297: ...n Function Pin Name 3 Wire Serial I O UART VPP1 Output Write voltage VPP VPP2 VDD I O VDD voltage generation voltage monitoring VDD Note Note GND Ground VSS CLK Output Clock output X1 RESET Output Reset signal RESET SI Input Receive signal SO20 TxD20 SO Output Transmit signal SI20 RxD20 SCK Output Transfer clock SCK20 HS Input Handshake signal Note VDD voltage must be supplied before programming i...

Page 298: ...connect the VPP pin as follows 1 Connect a pull down resistor of RVPP 10 kΩ to the VPP pin 2 Set the jumper on the board to switch the input of VPP pin to the programmer side or directly to GND The following shows an example of VPP pin connection Figure 17 4 VPP Pin Connection Example PD78F9436 78F9456 VPP µ Pull down resistor RVPP Connection pin of dedicated flash programmer Serial interface pins...

Page 299: ...h programmer Other device Input pin µ 2 Malfunction of another device When the dedicated flash programmer output or input is connected to a serial interface pin input or output connected to another device input a signal may be output to the device causing a malfunction To prevent such malfunction isolate the connection with other device or set so that the input signal to the device is ignored Figu...

Page 300: ...ns except those used for flash memory programming communication to the status immediately after reset Therefore if the external device does not acknowledge an initial status such as the output high impedance status connect the external device to VDD or VSS via a resistor Oscillation pins When using an on board clock connection of X1 X2 XT1 and XT2 must conform to the methods in the normal operatio...

Page 301: ...lash writing is used Figure 17 8 Wiring Example for Flash Writing Adapter Using 3 Wire Serial I O PD78F9436 GND VDD VDD2 LVDD SI SO SCK CLKOUT RESET VPP RESERVE HS WRITER INTERFACE VDD 2 7 to 5 5 V GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PD78F9456 µ µ ...

Page 302: ...er Using UART PD78F9436 GND VDD VDD2 LVDD SI SO SCK CLKOUT RESET VPP RESERVE HS WRITER INTERFACE VDD 2 7 to 5 5 V GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PD78F9456 µ µ ...

Page 303: ...ons Pull up resistor The connection of on chip pull up resistors for port 5 I O port can be switched in 1 bit units 1 Pull up resistor is connected 2 Pull up resistor is not connected RC oscillation RC oscillation is selectable for the main system clock 1 Crystal ceramic oscillation 2 RC oscillation Caution The flash memory products do not have mask options ...

Page 304: ...pecification Indirect address specification In the case of immediate data describe an appropriate numeric value or a label When using a label be sure to describe the and symbols For operand register identifiers r and rp either functional names X A C etc or absolute names names in parenthesis in the table below R0 R1 R2 etc can be used for description Table 19 1 Operand Identifiers and Description ...

Page 305: ... flag AC Auxiliary carry flag Z Zero flag IE Interrupt request enable flag NMIS Flag indicating non maskable interrupt servicing in progress Memory contents indicated by address or register contents in parenthesis XH XL Higher 8 bits and lower 8 bits of 16 bit register Logical product AND Logical sum OR V Exclusive logical sum exclusive OR Inverted data addr16 16 bit immediate data or label jdisp8...

Page 306: ... A 2 4 sfr A A addr16 3 8 A addr16 addr16 A 3 8 addr16 A PSW byte 3 6 PSW byte x x x A PSW 2 4 A PSW PSW A 2 4 PSW A x x x A DE 1 6 A DE DE A 1 6 DE A A HL 1 6 A HL HL A 1 6 HL A A HL byte 2 6 A HL byte HL byte A 2 6 HL byte A XCH A X 1 4 A X A r Note 2 2 6 A r A saddr 2 6 A saddr A sfr 2 6 A sfr A DE 1 8 A DE A HL 1 8 A HL A HL byte 2 8 A HL byte Notes 1 Except r A 2 Except r A X Remark One instr...

Page 307: ...HL byte 2 6 A CY A HL byte x x x ADDC A byte 2 4 A CY A byte CY x x x saddr byte 3 6 saddr CY saddr byte CY x x x A r 2 4 A CY A r CY x x x A saddr 2 4 A CY A saddr CY x x x A addr16 3 8 A CY A addr16 CY x x x A HL 1 6 A CY A HL CY x x x A HL byte 2 6 A CY A HL byte CY x x x SUB A byte 2 4 A CY A byte x x x saddr byte 3 6 saddr CY saddr byte x x x A r 2 4 A CY A r x x x A saddr 2 4 A CY A saddr x ...

Page 308: ...dr saddr byte x A r 2 4 A A r x A saddr 2 4 A A saddr x A addr16 3 8 A A addr16 x A HL 1 6 A A HL x A HL byte 2 6 A A HL byte x OR A byte 2 4 A A byte x saddr byte 3 6 saddr saddr byte x A r 2 4 A A r x A saddr 2 4 A A saddr x A addr16 3 8 A A addr16 x A HL 1 6 A A HL x A HL byte 2 6 A A HL byte x XOR A byte 2 4 A A V byte x saddr byte 3 6 saddr saddr V byte x A r 2 4 A A V r x A saddr 2 4 A A V s...

Page 309: ... x DEC r 2 4 r r 1 x x saddr 2 4 saddr saddr 1 x x INCW rp 1 4 rp rp 1 DECW rp 1 4 rp rp 1 ROR A 1 1 2 CY A7 A0 Am 1 Am 1 x ROL A 1 1 2 CY A0 A7 Am 1 Am 1 x RORC A 1 1 2 CY A0 A7 CY Am 1 Am 1 x ROLC A 1 1 2 CY A7 A0 CY Am 1 Am 1 x SET1 saddr bit 3 6 saddr bit 1 sfr bit 3 6 sfr bit 1 A bit 2 4 A bit 1 PSW bit 3 6 PSW bit 1 x x x HL bit 2 10 HL bit 1 CLR1 saddr bit 3 6 saddr bit 0 sfr bit 3 6 sfr bi...

Page 310: ...addr16 2 6 PC PC 2 jdisp8 if Z 1 BNZ saddr16 2 6 PC PC 2 jdisp8 if Z 0 BT saddr bit addr16 4 10 PC PC 4 jdisp8 if saddr bit 1 sfr bit addr16 4 10 PC PC 4 jdisp8 if sfr bit 1 A bit addr16 3 8 PC PC 3 jdisp8 if A bit 1 PSW bit addr16 4 10 PC PC 4 jdisp8 if PSW bit 1 BF saddr bit addr16 4 10 PC PC 4 jdisp8 if saddr bit 0 sfr bit addr16 4 10 PC PC 4 jdisp8 if sfr bit 0 A bit addr16 3 8 PC PC 3 jdisp8 ...

Page 311: ...te addr1 6 1 None A ADD ADDC SUB SUBC AND OR XOR CMP MOVNote XCHNote ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV ADD ADDC SUB SUBC AND OR XOR CMP MOV MOV XCH MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP ROR ROL RORC ROLC r MOV MOV INC DEC B C DBNZ sfr MOV MOV saddr MOV ADD ADDC SUB SUBC AND OR XOR CMP MOV DBNZ INC DEC a...

Page 312: ...ote saddrp SP None AX ADDW SUBW CMPW MOVW XCHW MOVW MOVW rp MOVW MOVW Note INCW DECW PUSH POP saddrp MOVW SP MOVW Note Only when rp BC DE or HL 3 Bit manipulation instructions SET1 CLR1 NOT1 BT BF 2nd Operand 1st Operand addr16 None A bit BT BF SET1 CLR1 sfr bit BT BF SET1 CLR1 saddr bit BT BF SET1 CLR1 PSW bit BT BF SET1 CLR1 HL bit SET1 CLR1 CY SET1 CLR1 NOT1 ...

Page 313: ...D 314 4 Call instructions branch instructions CALL CALLT BR BC BNC BZ BNZ DBNZ 2nd Operand 1st Operand AX addr16 addr5 addr16 Basic Instructions BR CALL BR CALLT BR BC BNC BZ BNZ Compound Instructions DBNZ 5 Other instructions RET RETI NOP EI DI HALT STOP ...

Page 314: ... 30 mA Output current low IOL Total for all pins 160 mA During normal operation 40 to 85 C Operating ambient temperature TA During flash memory programming 10 to 40 C Mask ROM version 65 to 150 C Storage temperature Tstg µPD78F9436 78F9456 40 to 125 C Notes 1 Make sure that the following conditions of the VPP voltage application timing are satisfied when the flash memory is written When supply vol...

Page 315: ...mum ratings are rated values at which the product is on the verge of suffering physical damage and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded Remarks 1 Unless otherwise specified the characteristics of alternate function pins are the same as those of port pins 2 The items in parentheses apply when RC oscillation is selected ma...

Page 316: ...ristics for instruction execution time 2 Time required to stabilize oscillation after reset or STOP mode release Cautions 1 When using the main system clock oscillator wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance Keep the wiring length as short as possible Do not cross the wiring with the other signal lines Do not ...

Page 317: ... the wiring length as short as possible Do not cross the wiring with the other signal lines Do not route the wiring near a signal line through which a high fluctuating current flows Always make the ground point of the oscillator capacitor the same potential as VSS Do not ground the capacitor to a ground pattern through which a high current flows Do not fetch signals from the oscillator 2 When the ...

Page 318: ...in the area enclosed by the broken lines in the above figure to avoid an adverse effect from wiring capacitance Keep the wiring length as short as possible Do not cross the wiring with the other signal lines Do not route the wiring near a signal line through which a high fluctuating current flows Always make the ground point of the oscillator capacitor the same potential as VSS Do not ground the c...

Page 319: ...0 0 3VDD V VIL1 P10 P11 P60 to P65 P70 to P72 P80 Note P81 Note P90 to P97 Note VDD 1 8 to 5 5 V 0 0 1VDD V VDD 2 7 to 5 5 V 0 0 3VDD V VIL2 P50 to P53 VDD 1 8 to 5 5 V 0 0 1VDD V VDD 2 7 to 5 5 V 0 0 2VDD V VIL3 RESET P00 to P03 P20 to P26 P30 to P33 VDD 1 8 to 5 5 V 0 0 1VDD V VDD 4 5 to 5 5 V 0 0 4 V Input voltage low VIL4 X1 CL1 X2 CL2 XT1 XT2 VDD 1 8 to 5 5 V 0 0 1 V VDD 4 5 to 5 5 V IOH 1 mA...

Page 320: ... VO VDD 3 µA Output leakage current low ILOL VO 0 V 3 µA Software pull up resistor R1 VI 0 V P00 to P03 P10 P11 P20 to P26 P30 to P33 P70 to P72 P80 Note 1 P81 Note 1 P90 to P97 Note 1 50 100 200 kΩ Mask option pull up resistor Note 3 R2 VI 0 V P50 to P53 10 30 60 kΩ Notes 1 µPD789425 789426 789435 789436 and 78F9436 only 2 If there is no on chip pull up resistor for P50 to P53 specified by the ma...

Page 321: ...erating mode Note 7 C1 C2 22 pF VDD 2 0 V 10 Note 3 0 6 1 25 mA VDD 5 0 V 10 1 65 3 0 mA VDD 3 0 V 10 0 65 1 44 mA IDD7 4 0 MHz RC oscillation operation mode R 4 7 kΩ C 22 pF VDD 2 0 V 10 0 38 1 05 mA VDD 5 0 V 10 1 1 2 29 mA VDD 3 0 V 10 0 6 1 28 mA IDD8 4 0 MHz RC oscillation HALT mode R 4 7 kΩ C 22 pF VDD 2 0 V 10 0 35 0 82 mA VDD 5 0 V 10 2 4 4 8 mA VDD 3 0 V 10 1 1 2 44 mA Power supply curren...

Page 322: ...5 µA VDD 5 0 V 10 0 1 17 µA VDD 3 0 V 10 0 05 5 5 µA IDD5 STOP mode Note 6 VDD 2 0 V 10 0 05 3 5 µA VDD 5 0 V 10 Note 2 5 2 10 8 mA VDD 3 0 V 10 Note 3 1 4 3 8 mA Power supply current Note 1 µPD78F9436 78F9456 IDD6 5 0 MHz crystal oscillation A D operating mode Note 7 C1 C2 22 pF VDD 2 0 V 10 Note 3 1 0 2 9 mA Notes 1 The port current including the current that flows to the on chip pull up resisto...

Page 323: ... clock 114 122 125 µs Capture input high low level width tCPTH tCPTL CPT90 10 µs VDD 2 7 to 5 5 V 0 4 MHz TMI60 input frequency fTMI VDD 1 8 to 5 5 V 0 275 kHz VDD 2 7 to 5 5 V 0 1 µs TMI60 input high low level width tTIMH tTIML VDD 1 8 to 5 5 V 1 8 µs Interrupt input high low level width tINTH tINTL INTP0 to INTP3 10 µs Key return input low level width tKRL KR0 to KR3 10 µs RESET low level width ...

Page 324: ...3 wire serial I O mode external clock input Parameter Symbol Conditions MIN TYP MAX Unit VDD 2 7 to 5 5 V 800 ns SCK20 cycle time tKCY2 VDD 1 8 to 5 5 V 3200 ns VDD 2 7 to 5 5 V 400 ns SCK20 high low level width tKH2 tKL2 VDD 1 8 to 5 5 V 1600 ns VDD 2 7 to 5 5 V 100 ns SI20 setup time to SCK20 tSIK2 VDD 1 8 to 5 5 V 150 ns VDD 2 7 to 5 5 V 400 ns SI20 hold time from SCK20 tKSI2 VDD 1 8 to 5 5 V 6...

Page 325: ...Parameter Symbol Conditions MIN TYP MAX Unit VDD 2 7 to 5 5 V 800 ns ASCK20 cycle time tKCY3 VDD 1 8 to 5 5 V 3200 ns VDD 2 7 to 5 5 V 400 ns ASCK20 high low level width tKH3 tKL3 VDD 1 8 to 5 5 V 1600 ns VDD 2 7 to 5 5 V 39063 bps Transfer rate VDD 1 8 to 5 5 V 9766 bps ASCK20 rise fall time tR tF 1 µs ...

Page 326: ...T1 inputs 0 8VDD 0 2VDD Point of measurement 0 8VDD 0 2VDD Clock Timing 1 fX tXL tXH X1 CL1 input VIH4 MIN VIL4 MAX 1 fXT tXTL tXTH XT1 input VIH5 MIN VIL5 MAX Capture Input Timing CPT90 tCPTL tCPTH TMI Timing 1 fTI tTIL tTIH TMI60 Interrupt Input Timing INTP0 to INTP3 tINTL tINTH Key Return Input Timing KR0 to KR3 tKRL ...

Page 327: ...Timing RESET tRSL Serial Transfer Timing 3 wire serial I O mode tKCYm tKLm tKHm SCK20 tSIKm tKSIm tKSOm Input data Output data SI20 SO20 Remark m 1 2 3 wire serial I O mode when using SS20 tKAS2 SO20 SS20 Output data tKDS2 UART mode external clock input tKCY3 tKL3 tKH3 ASCK20 tR tF ...

Page 328: ...rameter Symbol Conditions MIN TYP MAX Unit Resolution 10 10 10 bit 4 5 V AVDD 5 5 V 0 2 0 4 FSR 2 7 V AVDD 4 5 V 0 4 0 6 FSR Overall error Note 1 8 V AVDD 2 7 V 0 8 1 2 FSR 4 5 V AVDD 5 5 V 14 100 µs 2 7 V AVDD 4 5 V 19 100 µs Conversion time tCONV 1 8 V AVDD 2 7 V 28 100 µs 4 5 V AVDD 5 5 V 0 4 FSR 2 7 V AVDD 4 5 V 0 6 FSR Zero scale error Note AINL 1 8 V AVDD 2 7 V 1 2 FSR 4 5 V AVDD 5 5 V 0 4 F...

Page 329: ...IO 5 µA 0 0 2 V LCD output voltage differential Note 3 segment VODS IO 1 µA 0 0 2 V Notes 1 This is a capacitor that is connected between voltage pins used to drive the LCD C1 A capacitor connected between CAPH and CAPL C2 A capacitor connected between VLC0 and VSS C3 A capacitor connected between VLC1 and VSS C4 A capacitor connected between VLC2 and VSS 2 This is the wait time from when voltage ...

Page 330: ... Stabilization Wait Time TA 40 to 85 C VDD 1 8 to 5 5 V Parameter Symbol Conditions MIN TYP MAX Unit Crystal ceramic oscillation 2 15 fX s Release by RESET RC oscillation 2 7 fCC s Crystal ceramic oscillation Note 2 s Oscillation stabilization wait time Note 1 tWAIT Release by interrupt RC oscillation 2 7 fCC s Notes 1 Use a resonator whose oscillation stabilizes within the oscillation stabilizati...

Page 331: ... mA Write current Note VPP pin IPPW When VPP supply voltage VPP1 12 mA Erase current Note VDD pin IDDE When VPP supply voltage VPP1 During fX 5 0 MHz operation 7 mA Erase current Note VPP pin IPPE When VPP supply voltage VPP1 100 mA Unit erase time ter 0 5 1 1 s Total erase time tera 20 s Write count Erase write are regarded as 1 cycle 20 Times VPP0 In normal operation 0 0 2VDD V VPP supply voltag...

Page 332: ... the characteristics curves of the time from the start of voltage amplification VAON0 1 and the changes in the LCD output voltage when GAIN is set as 1 using the 3 V display panel 5 5 5 4 5 4 3 5 3 2 5 2 1 5 1 0 5 0 LCD output voltage V VDD4 5 V VDD5 V VDD5 5 V 0 500 1000 1500 2000 2500 3000 3500 4000 Voltage amplification time ms VLCD0 VLCD1 VLCD2 LCD output voltage Voltage amplification time ...

Page 333: ...llowing shows the temperature characteristics curves of LCD output voltage LCD output voltage V VLCD2 VLCD1 VLCD0 VLCD2 VLCD1 VLCD0 40 30 20 10 0 10 20 30 40 50 60 70 80 40 30 20 10 0 10 20 30 40 50 60 70 80 Temperature C LCD output voltage Temperature When GAIN 1 5 4 3 2 1 0 5 4 3 2 1 0 LCD output voltage V Temperature C LCD output voltage Temperature When GAIN 0 ...

Page 334: ... C 12 0 0 2 D F 1 125 14 0 0 2 B 12 0 0 2 N 0 10 P Q 0 1 0 05 1 0 S R 3 4 3 R H K J Q G I S P detail of lead end NOTE Each lead centerline is located within 0 13 mm of its true position T P at maximum material condition M H 0 32 0 06 0 10 I 0 13 J K 1 0 0 2 0 65 T P L 0 5 M 0 17 0 03 0 07 P64GK 65 9ET 3 T U 0 6 0 15 0 25 F M A B C D N T L U 1 1 0 1 ...

Page 335: ...ASTIC LQFP 10x10 ITEM MILLIMETERS A B D G 12 0 0 2 10 0 0 2 1 25 12 0 0 2 H 0 22 0 05 C 10 0 0 2 F 1 25 I J K 0 08 0 5 T P 1 0 0 2 L 0 5 P 1 4 Q 0 1 0 05 T 0 25 S 1 5 0 10 U 0 6 0 15 S64GB 50 8EU 2 R 3 4 3 N 0 08 M 0 17 0 03 0 07 A B C D U NOTE Each lead centerline is located within 0 08 mm of its true position T P at maximum material condition ...

Page 336: ...pin plastic TQFP 12 12 µPD789456GK 9ET 64 pin plastic TQFP 12 12 Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature 235 C Time 30 seconds max at 210 C or higher Count Two times or less Exposure limit 7 days Note after that prebake at 125 C for 10 hours IR35 107 2 VPS Package peak temperature 215 C Time 40 seconds max at 200 C or higher Count...

Page 337: ...re 350 C max Time 3 seconds max per pin row Caution Do not use different soldering methods together except for partial heating 3 µPD78F9436GK 9ET 64 pin plastic TQFP 12 12 µPD78F9456GK 9ET 64 pin plastic TQFP 12 12 µPD78F9436GB 8EU 64 pin plastic LQFP 10 10 µPD78F9456GB 8EU 64 pin plastic LQFP 10 10 Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak tem...

Page 338: ... 10 10 µPD789446GB 8EU A 64 pin plastic LQFP 10 10 µPD789455GB 8EU A 64 pin plastic LQFP 10 10 µPD789456GB 8EU A 64 pin plastic LQFP 10 10 µPD78F9436GK 9ET A 64 pin plastic TQFP 12 12 µPD78F9456GK 9ET A 64 pin plastic TQFP 12 12 µPD78F9436GB 8EU A 64 pin plastic LQFP 10 10 µPD78F9456GB 8EU A 64 pin plastic LQFP 10 10 Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflo...

Page 339: ...ries Figure A 1 shows development tools Support to PC98 NX Series Unless specified otherwise the products supported by IBM PC AT compatibles can be used in PC98 NX Series When using the PC98 NX Series refer to the explanation of IBM PC AT compatibles Windows Unless specified otherwise Windows indicates the following operating systems Windows 3 1 Windows 95 98 2000 Windows NT Ver 4 0 ...

Page 340: ... Language processing software Debugging software Control software Host machine PC or EWS Interface adapter Flash memory writing tools Flash programmer In circuit emulator Power supply unit Emulation board Emulation probe Target system Conversion socket or conversion adapter Flash memory writing adapter Flash memory Notes 1 The C library source file is not included in the software package 2 The pro...

Page 341: ...age RA78K0S Assembler package Part number µS RA78K0S Program that converts program written in C language into object codes that can be executed by a microcontroller Used in combination with an assembler package RA78K0S and device file DF789456 both sold separately Caution when used in PC environment The C compiler package is a DOS based application but may be used in the Windows environment by usi...

Page 342: ...ager Control software provided for efficient user program development in the Windows environment The project manager allows a series of tasks required for user program development to be performed including starting the editor building and starting the debugger Caution The project manager is included in the assembler package RA78K0S It cannot be used in an environment other than Windows A 4 Flash M...

Page 343: ...F A Interface adapter Adapter required when using a personal computer incorporating the PCI bus as the host machine IE 789456 NS EM1 Emulation board Emulation board for emulating the peripheral hardware inherent to the device Used in combination with an in circuit emulator NP 64GK NP H64GK TQ Emulation probe Probe for connecting the in circuit emulator and target system Used in combination with TG...

Page 344: ... simulating the operation of the target system on the host machine Using SM78K0S the logic and performance of the application can be verified independently of hardware development Therefore the development efficiency can be enhanced and the software quality can be improved Used in combination with a device file DF789456 sold separately SM78K0S System simulator Part number µS SM78K0S File containin...

Page 345: ...and TGK 064SBW are products of TOKYO ELETECH CORPORATION Table B 1 Distance Between IE System and Conversion Adapter Emulation Probe Conversion Adapter Distance Between IE System and Conversion Adapter NP 64GB TQ 170 mm NP H64GB TQ TGB 064SDP 370 mm NP 64GK 170 mm NP H64GK TQ TGK 064SBW 370 mm Figure B 1 Distance Between In Circuit Emulator and Conversion Adapter When 64GB Is Used 170 mm Note In c...

Page 346: ...tion probe NP 64GB TQ Emulation board IE 789456 NS EM1 22 mm 40 mm 34 mm Target system Conversion adapter TGB 064SDP 16 mm 16 mm 11 mm Figure B 3 Connection Conditions of Target System When NP H64GB TQ Is Used Emulation probe NP H64GB TQ Emulation board IE 789456 NS EM1 21 4 mm 42 6 mm 45 mm Target system Conversion adapter TGB 064SDP 16 mm 16 mm 11 mm ...

Page 347: ...A Emulation board IE 789456 NS EM1 Conversion adapter TGK 064SBW Target system CN1 Emulation probe NP 64GK NP H64GK TQ Note Distance when NP 64GK is used When NP H64GK TQ is used the distance is 370 mm Figure B 5 Connection Conditions of Target System When NP 64GK Is Used Emulation probe NP 64GK Emulation board IE 789456 NS EM1 21 95 mm 40 mm 34 mm Target system Conversion adapter TGK 064SBW 18 4 ...

Page 348: ...nual U15075EJ2V1UD 349 Figure B 6 Connection Conditions of Target System When NP H64GK TQ Is Used Emulation probe NP H64GK TQ Emulation board IE 789456 NS EM1 42 mm 45 mm 18 4 mm 11 mm Target system Conversion adapter TGK 064SBW 18 4 mm 21 95 mm 23 mm ...

Page 349: ...ontrol register 60 TCA60 148 E 8 bit compare register 50 CR50 141 8 bit compare register 60 CR60 141 8 bit compare register H60 CRH60 141 8 bit timer counter 50 TM50 142 8 bit timer counter 60 TM60 142 8 bit timer mode control register 50 TMC50 144 8 bit timer mode control register 60 TMC60 146 External interrupt mode register 0 INTM0 273 External interrupt mode register 1 INTM1 274 I Interrupt ma...

Page 350: ...or option register B2 PUB2 98 Pull up resistor option register B3 PUB3 98 Pull up resistor option register B7 PUB7 99 Pull up resistor option register B8 PUB8 99 Pull up resistor option register B9 PUB9 100 R Receive buffer register 20 RXB20 217 S Serial operation mode register 20 CSIM20 218 225 228 241 Subclock control register CSS 107 Suboscillation mode register SCKM 106 16 bit capture register...

Page 351: ...CR60 8 bit compare register 60 141 CR90 16 bit compare register 90 122 CRH60 8 bit compare register H60 141 CSIM20 Serial operation mode register 20 218 225 228 241 CSS Subclock control register 107 I IF0 Interrupt request flag register 0 271 IF1 Interrupt request flag register 1 271 INTM0 External interrupt mode register 0 273 INTM1 External interrupt mode register 1 274 K KRM00 Key return mode r...

Page 352: ...ster B3 98 PUB7 Pull up resistor option register B7 99 PUB8 Pull up resistor option register B8 99 PUB9 Pull up resistor option register B9 100 R RXB20 Receive buffer register 20 217 S SCKM Suboscillation mode register 106 T TCA60 Carrier generator output control register 60 148 TCP90 16 bit capture register 90 122 TM50 8 bit timer counter 50 142 TM60 8 bit timer counter 60 142 TM90 16 bit timer c...

Page 353: ...imer Mode Control Register 50 Modification of Figure 7 5 Format of 8 Bit Timer Mode Control Register 60 Addition of Cautions to Figure 7 6 Format of Carrier Generator Output Control Register 60 Modification of Table 7 3 Interval Time of Timer 50 Modification of Table 7 4 Interval Time of Timer 60 Modification of Table 7 5 Square Wave Output Range of Timer 50 During fX 5 0 MHz Operation Modificatio...

Page 354: ... CHAPTER 23 RECOMMENDED SOLDERING CONDITIONS Total revision of appendix APPENDIX A DEVELOPMENT TOOLS Addition of appendix APPENDIX B NOTES ON TARGET SYSTEM DESIGN APPENDIX D REVISION HISTORY Deletion of APPENDIX B EMBEDDED SOFTWARE Addition of lead free products CHAPTER 1 GENERAL 2nd modification version Addition of soldering conditions of lead free products in Table 23 1 Surface Mounting Type Sol...

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