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CHAPTER 5 CLOCK GENERATOR
User’s Manual U15075EJ2V1UD
105
(1) Processor clock control register (PCC)
PCC sets CPU clock selection and the division ratio.
PCC is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets PCC to 02H.
Figure 5-2. Format of Processor Clock Control Register
Control of main system clock oscillator operation
MCC
0
0
0
0
0
PCC1
0
PCC
Symbol
Address
After reset
R/W
FFFBH
02H
R/W
<7>
6
5
4
3
2
1
0
MCC
0
1
Operation enabled
Operation disabled
CPU clock (f
CPU
) selection
Note
At f
X
= 5.0 MHz operation, f
XT
= 32.768 kHz operation
At f
CC
= 4.0 MHz operation, f
XT
= 32.768 kHz operation
CSS0
0
0
1
1
PCC1
0
1
0
1
f
X
(0.2 s)
f
X
/2
2
(0.8 s)
f
XT
/2 (61 s)
f
CC
(0.25 s)
f
CC
/2
2
(1.0 s)
µ
µ
µ
µ
µ
Note
The CPU clock is selected according to a combination of the PCC1 flag in the processor clock control
register (PCC) and the CSS0 flag in the subclock control register (CSS) (Refer to
5.3 (3) Subclock control
register (CSS)
).
Cautions 1. Bits 0 and 2 to 6 must be set to 0.
2. The MCC can be set only when the subsystem clock has been selected as the CPU clock.
Remarks 1.
f
X
: Main system clock oscillation frequency (crystal/ceramic oscillation)
2.
f
CC
: Main system clock oscillation frequency (RC oscillation)
3.
f
XT
: Subsystem clock oscillation frequency
CPU clock (f
CPU
)
×
2 indicates the minimum instruction execution time. The following table shows minimum
instruction execution time based on each setting value.
Minimum instruction execution time
CSS0 PCC1
At f
X
= 5.0 MHz operation,
f
XT
= 32.768 kHz operation
At f
CC
= 4.0 MHz operation,
f
XT
= 32.768 kHz operation
0 0
0.4
µ
s 0.5
µ
s
0 1
1.6
µ
s 2.0
µ
s
1 0
1 1
122
µ
s