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CHAPTER 8 USB FUNCTION

User’s Manual U12978EJ3V0UD

116

(7) Handshake packet transmit reservation register (HTXRSV)

This register sets the handshake packet to be transmitted. By setting each flag of this register, a handshake

packet is transmitted following normal reception of an IN packet, or normal or abnormal reception of a data

packet.

Bit 0 corresponds to the ACK packet transmit reservation flag, bits 1 to 3 correspond to the NAK packet transmit

reservation flag, and bits 4 to 7 correspond to the STALL packet transmit reservation flag.

HTXRSV is set with a 1-bit or 8-bit memory manipulation instruction. When HTXRSV is used in combination

with the data packet transmit reservation register (DTXRSV) as the 16-bit register USBCON, HTXRSV is set

with a 16-bit memory manipulation instruction.

RESET input sets HTXRSV to 00H.

SETUP reception

Note

also sets HTXRSV to 00H.

Note

SETUP reception implies the satisfaction of all the following three conditions.

•

Matching of address

•

Endpoint 0 received

•

No error in reception

Figure 8-16. Format of Handshake Packet Transmit Reservation Register (1/2)

Symbol

E1STEN E0STEN

DSTEN STALEN E1NAEN E0NAEN DNAEN

ACKEN

E1STEN

STALL packet transmit reservation flag for Endpoint 1 after IN packet

FF14H

Address

HTXRSV

After reset

00H

R/W

No data is transmitted.

STALL handshake is transmitted when all the following conditions are satisfied in EOP during IN packet reception.

INRX (internal signal) = 1, ADRRST = 1, END1RX = 1, TBYER = 0, TBITER = 0, CRC5ER = 0

E0STEN

STALL packet transmit reservation flag for Endpoint 0 after IN packet

No data is transmitted.

STALL handshake is transmitted when all the following conditions are satisfied in EOP during IN packet reception.

INRX (internal signal) = 1, TIDRST = 1, ADRRST = 1, END0RX = 1, TBYER = 0, TBITER = 0, CRC5ER = 0

STALEN

STALL packet transmit reservation flag after data packet

No data is transmitted.

STALL handshake is transmitted when all the following conditions are satisfied in EOP during data packet reception.

Set this flag when length error of transfer occurs in control write transfer.

DIDRST = 0, DBITER = 0

DSTEN

STALL packet transmitted reservation flag for data packet receive byte length error

No data is transmitted.

STALL handshake is transmitted when all the following conditions are satisfied in EOP during data packet reception.

Set this flag to transmit STALL handshake when byte length error has occurred in one data packet during

control write transfer.

DIDRST = 1, DBYER = 1, DBITER = 0

Summary of Contents for switch

Page 1: ... s Manual µ µ µ µPD789800 µ µ µ µPD78F9801 µ µ µ µPD789800 Subseries 8 Bit Single Chip Microcontrollers Printed in Japan Document No U12978EJ3V0UD00 3rd edition Date Published February 2003 N CP K 1998 2003 ...

Page 2: ...User s Manual U12978EJ3V0UD 2 MEMO ...

Page 3: ...s behave differently than Bipolar or NMOS devices Input levels of CMOS devices must be fixed high or low by using a pull up or pull down circuitry Each unused pin should be connected to VDD or GND with a resistor if it is considered to have a possibility of being an output pin All handling related to the unused pins must be judged device by device and related specifications governing the devices 3...

Page 4: ...afety of NEC Electronics products customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely To minimize risks of damage to property or injury including death to persons arising from defects in NEC Electronics products customers must incorporate sufficient safety measures in their design such as redundancy fire containment and anti failure features NEC El...

Page 5: ...1 6841 1138 Fax 021 6841 1137 NEC Electronics Taiwan Ltd Taipei Taiwan Tel 02 2719 2377 Fax 02 2719 5951 NEC Electronics Singapore Pte Ltd Novena Square Singapore Tel 6253 8311 Fax 6250 3583 J02 11 NEC Electronics Europe GmbH Duesseldorf Germany Tel 0211 65 03 01 Fax 0211 65 03 327 Sucursal en España Madrid Spain Tel 091 504 27 87 Fax 091 504 28 60 Vélizy Villacoublay France Tel 01 30 67 58 00 Fax...

Page 6: ...re register TRXRSL Addition of Caution for data packet transmit reservation register DTXRSV Modification of description of bit 1 DNAEN of handshake packet transmit reservation register HTXRSV Change of contents of 8 5 2 Remote wakeup control operation Addition of Table 8 4 List of Sources of Interrupts from USB Function Correction of incorrect flag name in 8 6 Interrupt Request from USB Function A...

Page 7: ...f electrical engineering logic circuits and microcontrollers To understand the overall functions of the µPD789800 Subseries Read this manual in the order of the CONTENTS How to read register formats The name of a bit whose number is enclosed in angle brackets is reserved in the assembler and is defined in the C compiler by the header file sfrbit h To learn the detailed functions of a register whos...

Page 8: ...wsTM Based U15373E SM78K Series System Simulator Ver 2 30 or Later External Part User Open Interface Specifications U15802E ID78K Series Integrated Debugger Ver 2 30 or Later Operation Windows Based U15185E Project Manager Ver 3 12 or Later Windows Based U14610E Documents Related to Development Tools Hardware User s Manuals Document Name Document No IE 78K0S NS In Circuit Emulator U13549E IE 78K0S...

Page 9: ...Technology Manual C10535E Quality Grades on NEC Semiconductor Devices C11531E NEC Semiconductor Device Reliability Quality Control System C10983E Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge ESD C11892E Caution The related documents listed above are subject to change without notice Be sure to use the latest version of each document for designing ...

Page 10: ... 31 2 2 9 USBDP 31 2 2 10 VDD0 VDD1 31 2 2 11 VSS0 VSS1 31 2 2 12 VPP µPD78F9801 only 32 2 2 13 IC mask ROM version only 32 2 3 Pin I O Circuits and Recommended Connection of Unused Pins 33 CHAPTER 3 CPU ARCHITECTURE 35 3 1 Memory Space 35 3 1 1 Internal program memory space 37 3 1 2 Internal data memory internal high speed RAM space 37 3 1 3 Special function register SFR area 37 3 1 4 Data memory...

Page 11: ...or Functions 73 5 2 Clock Generator Configuration 73 5 3 Register Controlling Clock Generator 74 5 4 System Clock Oscillators 75 5 4 1 System clock oscillator 75 5 4 2 Examples of incorrect resonator connection 76 5 4 3 Frequency divider 77 5 5 Clock Generator Operation 77 5 6 Changing Setting of CPU Clock 78 5 6 1 Time required for switching CPU clock 78 5 6 2 Switching CPU clock 78 CHAPTER 6 8 B...

Page 12: ...nd operation modes 130 8 7 2 Interrupt servicing flow 136 8 8 USB Function Internal Circuit Operations 140 8 8 1 Operation of transmit receive pointer 140 8 8 2 Receive bank switching ID detection buffer operation 147 8 8 3 Sync detection USBCLK detector operation 148 8 8 4 NRZI encoder operation 150 8 8 5 Bit stuffing strip controller operation 151 CHAPTER 9 SERIAL INTERFACE 10 154 9 1 Functions ...

Page 13: ...4 1 3 On board pin processing 195 14 1 4 Connection of adapter for flash writing 198 CHAPTER 15 INSTRUCTION SET 200 15 1 Operation 200 15 1 1 Operand identifiers and description methods 200 15 1 2 Description of operation column 201 15 1 3 Description of flag operation column 201 15 2 Operation List 202 15 3 Instructions Listed by Addressing Type 207 CHAPTER 16 ELECTRICAL SPECIFICATIONS 210 CHAPTE...

Page 14: ...User s Manual U12978EJ3V0UD 14 B 1 Register Index Alphabetic Order of Register Name 229 B 2 Register Index Alphabetic Order of Register Symbol 231 APPENDIX C REVISION HISTORY 233 ...

Page 15: ...k Diagram of P22 64 4 7 Block Diagram of P23 and P24 65 4 8 Block Diagram of P25 66 4 9 Block Diagram of P26 67 4 10 Block Diagram of P40 to P47 68 4 11 Format of Port Mode Register 69 4 12 Format of Pull up Resistor Option Register 0 70 4 13 Format of Port Output Mode Register 0 71 4 14 Format of Port Output Mode Register 1 71 5 1 Block Diagram of Clock Generator 73 5 2 Format of Processor Clock ...

Page 16: ...cket Receive Mode Register 110 8 12 Format of Packet Receive Status Register 112 8 13 Format of Data Handshake Packet Receive Result Store Register 113 8 14 Format of Token Packet Receive Result Store Register 114 8 15 Format of Data Packet Transmit Reservation Register 115 8 16 Format of Handshake Packet Transmit Reservation Register 116 8 17 Configuration of Handshake Packet Transmit Reservation...

Page 17: ...70 11 8 Flowchart of Non Maskable Interrupt Request Acknowledgment 172 11 9 Timing of Non Maskable Interrupt Request Acknowledgment 172 11 10 Acknowledging Non Maskable Interrupt Request 172 11 11 Interrupt Acknowledgment Program Algorithm 173 11 12 Timing of Interrupt Request Acknowledgment Example of MOV A r 174 11 13 Timing of Interrupt Request Acknowledgment When Interrupt Request Flag Is Gene...

Page 18: ...of Serial Interface 196 14 6 Abnormal Operation of Other Device 196 14 7 Signal Conflict RESET Pin 197 14 8 Wiring Example for Flash Writing Adapter with 3 Wire Serial I O 198 14 9 Wiring Example for Flash Writing Adapter with Pseudo 3 Wire Method 199 A 1 Development Tools 222 A 2 Distance Between In Circuit Emulator and Conversion Adapter 227 A 3 Connection Condition of Target System NP H44GB TQ ...

Page 19: ...6 6 Interval Time of 8 Bit Timer Event Counter 01 85 6 7 Square Wave Output Range of 8 Bit Timer Event Counter 01 88 7 1 Inadvertent Loop Detection Time of Watchdog Timer 91 7 2 Interval Time 91 7 3 Configuration of Watchdog Timer 92 7 4 Inadvertent Loop Detection Time of Watchdog Timer 95 7 5 Interval Time of Interval Timer 96 8 1 Configuration of USB Function 98 8 2 Flag of RXSTAT After Receptio...

Page 20: ... 4 Operation After Release of STOP Mode 185 13 1 Hardware Status After Reset 188 14 1 Differences Between µPD78F9801 and Mask ROM Versions 190 14 2 Communication Mode List 192 14 3 Pin Connection List 194 15 1 Operand Identifiers and Description Methods 200 18 1 Surface Mounting Type Soldering Conditions 220 ...

Page 21: ...d 0 33 µs to low speed 1 33 µs with the system clock operating at 6 0 MHz 31 I O ports Two serial interface channels USB function 3 wire serial I O mode Three timers 8 bit timer 8 bit timer event counter Watchdog timer On chip key return signal detector 12 vectored interrupt sources Power supply voltage VDD 4 0 to 5 5 V Operating ambient temperature TA 40 to 85 C when the USB is not operating TA 0...

Page 22: ...30 29 28 27 26 25 24 23 Cautions 1 Connect the IC pin directly to the VSS0 pin 2 Directly connect the VPP pin to the VSS0 pin in the normal operation mode Remark The parenthesized values apply to the µPD78F9801 IC Internally connected SI10 Serial data input INTP0 Interrupt from peripherals SO10 Serial data output KR00 to KR07 Key return TI01 Timer input NC No connection TO01 Timer output P00 to P0...

Page 23: ... PD789156 44 pin Small scale package general purpose applications and A D function 44 pin 30 pin 30 pin 30 pin 30 pin PD789124A PD789134A PD789177 PD789167 30 pin 30 pin PD789104A PD789114A PD789167 with 10 bit A D PD789104A with enhanced timer PD789124A with 10 bit A D RC oscillation version of PD789104A PD789104A with 10 bit A D PD789026 with 8 bit A D and multiplier added PD789104A with EEPROMT...

Page 24: ...ch 1 ch 8 ch 31 µPD789156 4 ch µPD789146 8 K to 16 K 4 ch On chip EEPROM µPD789134A 4 ch µPD789124A 4 ch RC oscillation version µPD789114A 4 ch Small scale package general purpose applica tions A D converter µPD789104A 2 K to 8 K 1 ch 1 ch 1ch 4 ch 1 ch UART 1ch 20 1 8 V µPD789835 24 K to 60 K 6 ch 3 ch 37 1 8 VNote µPD789830 24 K 1 ch 1 ch UART 1ch 30 2 7 V Dot LCD supported µPD789489 32 K to 48 ...

Page 25: ... 16 K 3 ch Note 1 1 ch 1 ch 8 ch 1 ch UART 1ch 30 4 0 V On chip bus controller µPD789850 16 K 1 ch 1 ch 1 ch 4 ch 2 ch UART 1ch 18 4 0 V µPD789861 1 8 V RC oscillation version on chip EEPROM µPD789860 4 K 2 ch 1 ch 14 Keyless entry µPD789862 16 K 1 ch 2 ch 1 ch UART 1ch 22 On chip EEPROM VFD drive µPD789871 4 K to 8 K 3 ch 1 ch 1 ch 1 ch 33 2 7 V Meter control µPD789881 16 K 2 ch 1 ch 1 ch 1 ch UA...

Page 26: ...nction 0 Serial interface 1 Interrupt control Port 0 Port 1 Port 2 Port 4 System control 78K 0S CPU core ROM Flash memory RAM P00 to P07 P10 to P17 P20 to P26 P40 to P47 RESET X1 X2 KR00 to KR07 TI01 TO01 P26 INTP0 REGC USBDM USBDP SCK10 P20 SO10 P21 SI10 P22 INTP0 P26 VDD0 VDD1 VSS0 VSS1 IC VPP VREG Remark The parenthesized values apply to the µPD78F9801 ...

Page 27: ... channel Regulator Incorporated VREG 3 3 0 3 V Maskable Internal 9 external 2 Vector interrupt sources Non maskable Internal 1 Power supply voltage VDD 4 0 to 5 5 V Operating ambient temperature TA 40 to 85 C when the USB is not operating TA 0 to 70 C when the USB is operating TA 10 to 40 C when a flash memory is written Package 44 pin plastic LQFP 10 10 An outline of the timer is shown below 8 Bi...

Page 28: ...tors can be specified by pull up resistor option register 0 PU0 When used as an output port CMOS output or N ch open drain output can be specified in 8 bit units by port output mode register 0 POM0 Input P20 SCK10 P21 SO10 P22 SI10 P23 to P25 P26 I O Port 2 7 bit I O port Input output can be specified in 1 bit units When used as an input port use of on chip pull up resistors can be specified by pu...

Page 29: ...ce Input P22 SO10 Output Serial data output for serial interface Input P21 TI01 Input External count clock input to 8 bit timer TM01 Input P26 INTP0 TO01 TO01 Output Output from 8 bit timer TM01 Input P26 INTP0 TI01 USBDM I O Serial data input output negative side for USB function The pull up resistor 1 5 kΩ for the USBDM pin must be connected to the REGC pin Input USBDP I O Serial data input outp...

Page 30: ...O to and from the serial interface external interrupt input and timer I O Port 2 can be specified in the following operation modes in 1 bit units 1 Port mode In the port mode P20 to P26 function as a 7 bit I O port Port 2 can be set to the input or output mode in 1 bit units by using port mode register 2 PM2 When the port is used as an input port an on chip pull up resistor can be used by setting ...

Page 31: ... this mode the pins function as key return signal detection pins KR00 to KR07 2 2 5 RESET This pin inputs an active low system reset signal 2 2 6 X1 X2 These pins are used to connect a crystal resonator for system clock oscillation To supply an external clock input the clock to X1 and input the inverted signal to X2 2 2 7 REGC This pin is a power supply pin for driving a USB driver receiver genera...

Page 32: ...ramming mode or to VSS0 in normal operation mode using a jumper on the board 2 2 13 IC mask ROM version only The IC Internally Connected pin is used to set the µPD789800 Subseries in the test mode before shipment In the normal operation mode directly connect this pin to the VSS0 pin with as short a wiring length as possible If a potential difference is generated between the IC pin and VSS0 pin due...

Page 33: ...ed Pins Pin Name I O Circuit Type I O Recommended Connection of Unused Pins P00 to P07 P10 to P17 5 R P20 SCK10 P21 SO10 P22 SI10 P23 P24 8 C P25 P26 INTP0 TI01 TO01 8 F P40 KR00 to P47 KR07 8 C Input Independently connect to VDD0 VDD1 VSS0 or VSS1 via a resistor Output Leave open USBDM Connect to the REGC pin USBDP 24 A I O Independently connect to VSS0 or VSS1 via a resistor RESET 2 Input NC Lea...

Page 34: ...input with hysteresis characteristics Pull up enable P ch cut Output data Output disable VDD0 VDD0 P ch N ch IN OUT P ch Input enable VSS0 VDD0 P ch IN OUT P ch VDD0 Pull up enable Output disable Output data N ch VSS0 Pull up enable P ch cut Output data Output disable VDD0 VDD0 P ch N ch IN OUT P ch VSS0 VSS0 TXDXP RXDX TXDXN VREG P ch N ch IN OUT ...

Page 35: ...ry Map µ µ µ µPD789800 Reserved Internal ROM 8 192 8 bits Internal high speed RAM 256 8 bits Special function register 256 8 bits H F F F F H 0 0 F F H F F E F H 0 0 E F H F F D F H F F F 1 H 0 8 0 0 H F 7 0 0 H 0 4 0 0 H F 3 0 0 H A 1 0 0 H 9 1 0 0 H 0 0 0 0 H 0 0 0 2 H 0 0 0 0 Data memory space Program memory space Program area CALLT table area Vector table area Program area H F F F 1 ...

Page 36: ...s Internal high speed RAM 256 8 bits Special function register 256 8 bits H F F F F H 0 0 F F H F F E F H 0 0 E F H F F D F H F F F 3 H 0 8 0 0 H F 7 0 0 H 0 4 0 0 H F 3 0 0 H A 1 0 0 H 9 1 0 0 H 0 0 0 0 H 0 0 0 4 H 0 0 0 0 Data memory space Program memory space Program area CALLT table area Vector table area Program area H F F F 3 ...

Page 37: ...tored in an odd address Table 3 1 Vector Table Vector Table Address Interrupt Request Vector Table Address Interrupt Request 0000H RESET input 000EH INTUSBRE 0004H INTWDT 0010H INTP0 0006H INTUSBTM 0012H INTCSI10 0008H INTUSBRT 0014H INTTM00 000AH INTUSBRD 0016H INTTM01 000CH INTUSBST 0018H INTKR00 2 CALLT instruction table area The subroutine entry address of a 1 byte call instruction CALLT can b...

Page 38: ...s are possible to meet the functions of the special function registers SFR and general purpose registers Figures 3 3 and 3 4 show the data memory addressing modes Figure 3 3 Data Memory Addressing µ µ µ µPD789800 Special function registers SFR 256 8 bits Internal high speed RAM 256 8 bits Internal ROM 8 192 8 bits FFFFH 0000H Direct addressing Register indirect addressing Based addressing FF00H FE...

Page 39: ... µPD78F9801 Special function registers SFR 256 8 bits Internal high speed RAM 256 8 bits Flash memory 16 384 8 bits FFFFH 0000H Direct addressing Register indirect addressing Based addressing FF00H FEFFH FF20H FF1FH FE20H FE1FH SFR addressing Short direct addressing Reserved FE00H FDFFH 4000H 3FFFH ...

Page 40: ...bytes of the instruction to be fetched When a branch instruction is executed immediate data or register contents are set RESET input sets the program counter to the reset vector table values at addresses 0000H and 0001H Figure 3 5 Configuration of Program Counter PC15 PC PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 15 0 2 Program status word PSW The program status word is an 8 ...

Page 41: ...sponding to each interrupt source The IE flag is reset 0 upon DI instruction execution or interrupt acknowledgment and is set 1 upon EI instruction execution b Zero flag Z When the operation result is zero this flag is set 1 It is reset 0 in all other cases c Auxiliary carry flag AC If the operation result has a carry from bit 3 or a borrow at bit 3 this flag is set 1 It is reset 0 in all other ca...

Page 42: ...res data as shown in Figures 3 8 and 3 9 Caution Since RESET input makes the SP contents undefined be sure to initialize the SP before instruction execution Figure 3 8 Data to Be Saved to Stack Memory Interrupt PSW PC15 to PC8 PC15 to PC8 PC7 to PC0 Lower half register pairs SP SP _ 2 SP _ 2 CALL CALLT instructions PUSH rp instruction SP _ 1 SP SP SP _ 2 SP _ 2 SP _ 1 SP PC7 to PC0 SP _ 3 SP _ 2 S...

Page 43: ...bit registers in pairs can be used as a 16 bit register AX BC DE and HL They can be described in terms of functional names X A C B E D L H AX BC DE and HL and absolute names R0 to R7 and RP0 to RP3 Figure 3 10 Configuration of General Purpose Registers a Absolute names R0 15 0 7 0 16 bit processing 8 bit processing RP3 RP2 RP1 RP0 R1 R2 R3 R4 R5 R6 R7 b Functional names X 15 0 7 0 16 bit processin...

Page 44: ...tion operand sfr This manipulation can also be specified using an address 16 bit manipulation Describe the symbol reserved by the assembler for the 16 bit manipulation instruction operand When specifying an address describe an even address Table 3 2 lists the special function registers The meanings of the symbols in this table are as follows Symbol Indicates the address of the implemented special ...

Page 45: ...ft register 10 SIO10 R W FF14H Handshake packet transmit reservation register HTX RSV USB CON 00H FF15H Data packet transmit reservation register DTX RSV FF20H Port mode register 0 PM0 FFH FF21H Port mode register 1 PM1 FF22H Port mode register 2 PM2 FF24H Port mode register 4 PM4 FF30H Port output mode register 0 POM0 00H FF31H Port output mode register 1 POM1 FF42H Timer clock select register 2 ...

Page 46: ...ion mode register 10 CSIM10 FFA1H Transmit data PID bank 0 USBTD0 W Undefined FFA2H Transmit data bank 0 address 00 USBT00 FFA3H Transmit data bank 0 address 01 USBT01 FFA4H Transmit data bank 0 address 02 USBT02 FFA5H Transmit data bank 0 address 03 USBT03 FFA6H Transmit data bank 0 address 04 USBT04 FFA7H Transmit data bank 0 address 05 USBT05 FFA8H Transmit data bank 0 address 06 USBT06 FFA9H T...

Page 47: ...ol R W Manipulatable Bit Unit After Reset 1 Bit 8 Bits 16 Bits FFECH External interrupt mode register 0 INTM0 R W 00H FFF5H Key return mode register 00 KRM00 FFF7H Pull up resistor option register 0 PU0 FFF9H Watchdog timer mode register WDTM FFFAH Oscillation stabilization time select register OSTS 04H FFFBH Processor clock control register PCC 02H ...

Page 48: ...sing Function The value obtained by adding 8 bit immediate data displacement value jdisp8 of an instruction code to the start address of the following instruction is transferred to the program counter PC and branched The displacement value is treated as signed two s complement data 128 to 127 and bit 7 becomes a sign bit This means that information is relatively branched to a location between 128 ...

Page 49: ...ansferred to the program counter PC and branched This function is carried out when the CALL addr16 or BR addr16 instruction is executed The CALL addr16 and BR addr16 instructions can be branched to any location in the memory space Illustration In case of CALL addr16 and BR addr16 instructions 15 0 PC 8 7 7 0 CALL or BR Low Addr High Addr ...

Page 50: ...cuted The instruction enables a branch to any location in the memory space by referring to the addresses stored in the memory table at 40H to 7FH Illustration 15 1 15 0 PC 7 0 Low Addr High Addr Memory Table Effective address 1 Effective address 0 1 0 0 0 0 0 0 0 0 8 7 8 7 6 5 0 0 0 0 1 7 6 5 1 0 ta4 0 Instruction code 3 3 4 Register addressing Function Register pair AX contents to be specified wi...

Page 51: ...truction execution 3 4 1 Direct addressing Function The memory indicated by immediate data in an instruction word is directly addressed Operand format Identifier Description addr16 Label or 16 bit immediate data Description example MOV A FE00H When setting addr16 to FE00H Instruction code 0 0 1 0 1 0 0 1 Opcode 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 00H FEH Illustration 7 0 Opcode addr16 Low addr16 High ...

Page 52: ...er of the timer event counter are mapped and these SFRs can be manipulated with a small number of bytes and clocks When 8 bit immediate data is at 20H to FFH bit 8 of an effective address is set to 0 When it is at 00H to 1FH bit 8 is set to 1 See Illustration below Operand format Identifier Description saddr Label or FE20H to FF1FH immediate data saddrp Label or FE20H to FF1FH immediate data even ...

Page 53: ...is addressing is applied to the 240 byte spaces FF00H to FFCFH and FFE0H to FFFFH However the SFR mapped at FF00H to FF1FH can be accessed with short direct addressing Operand format Identifier Description sfr Special function register name Description example MOV PM0 A When selecting PM0 for sfr Instruction code 1 1 1 0 0 1 1 1 0 0 1 0 0 0 0 0 Illustration 15 0 SFR Effective Address 1 1 1 1 1 1 1...

Page 54: ...erand format is executed When an 8 bit register is specified one of the eight registers is specified with 3 bits in the instruction code Operand format Identifier Description r X A C B E D L H rp AX BC DE HL r and rp can be described by absolute names R0 to R7 and RP0 to RP3 as well as function names X A C B E D L H AX BC DE and HL Description example MOV A C When selecting the C register for r In...

Page 55: ...The register pair to be accessed is specified by the register pair specification code in an instruction code This addressing can be carried out for all the memory spaces Operand format Identifier Description DE HL Description example MOV A DE When selecting register pair DE Instruction code 0 0 1 0 1 0 1 1 Illustration 15 0 8 D 7 E 0 7 7 0 A DE Addressed memory contents are transferred Memory addr...

Page 56: ...ces Operand format Identifier Description HL byte Description example MOV A HL 10H When setting byte to 10H Instruction code 0 0 1 0 1 1 0 1 0 0 0 1 0 0 0 0 3 4 7 Stack addressing Function The stack area is indirectly addressed with the stack pointer SP contents This addressing method is automatically employed when the PUSH POP subroutine call and RETURN instructions are executed or the register i...

Page 57: ... shown in Figure 4 1 enabling various methods of control Numerous other functions are provided that can be used in addition to the digital I O port functions For more information on these additional functions see CHAPTER 2 PIN FUNCTIONS Figure 4 1 Port Types P20 P26 P40 P47 P10 P17 Port 2 Port 4 Port 1 P00 P07 Port 0 ...

Page 58: ...can be specified by pull up resistor option register 0 PU0 When used as an output port CMOS output or N ch open drain output can be specified in 8 bit units by port output mode register 0 POM0 Input P20 SCK10 P21 SO10 P22 SI10 P23 P24 P25 P26 I O Port 2 7 bit I O port Input output can be specified in 1 bit units When used as an input port use of on chip pull up resistors can be specified by pull u...

Page 59: ...llowing hardware Table 4 2 Configuration of Port Parameter Configuration Control registers Port mode register PMm m 0 to 2 4 Pull up resistor option register PU0 Port output mode register POMm m 0 1 Ports Total 31 N ch open drain output is specifiable for 18 ports Pull up resistors Software control 31 ...

Page 60: ...option register 0 PU0 CMOS output or N ch open drain output can also be specified in 8 bit unit by using port output mode register 0 POM0 Port 0 is set in the input mode when the RESET signal is input Figure 4 2 shows a block diagram of port 0 Figure 4 2 Block Diagram of P00 to P07 RD VDD0 P00 to P07 WRPU0 WRPORT WRPM Output latch P00 to P07 PM00 to PM07 PU00 P ch P ch N ch VDD0 POM00 Internal bus...

Page 61: ...option register 0 PU0 CMOS output or N ch open drain output can also be specified in 8 bit unit by using port output mode register 0 POM0 Port 0 is set in the input mode when the RESET signal is input Figure 4 3 shows a block diagram of port 1 Figure 4 3 Block Diagram of P10 to P17 POM0 Port output mode register 0 PU0 Pull up resistor option register 0 PM Port mode register RD Port 1 read signal W...

Page 62: ...register 1 POM1 The port is also used as a data I O and clock I O to and from the serial interface timer I O and external interrupt This port to set to the input mode when the RESET signal is input Figures 4 4 through 4 9 show block diagrams of port 2 Caution When using the pins of port 2 as the serial interface the I O or output latch must be set according to the function to be used For how to se...

Page 63: ...UD 63 Figure 4 5 Block Diagram of P21 PU0 Pull up resistor option register 0 PM Port mode register RD Port 2 read signal WR Port 2 write signal Internal bus VDD0 P ch P21 SO10 WRPU0 RD WRPORT WRPM PU02 Output latch P21 PM21 Alternate function Selector ...

Page 64: ...UD 64 Figure 4 6 Block Diagram of P22 PU0 Pull up resistor option register 0 PM Port mode register RD Port 2 read signal WR Port 2 write signal Internal bus VDD0 P ch P22 SI10 WRPU0 RD WRPORT WRPM PU02 Alternate function Output latch P22 PM22 Selector ...

Page 65: ...V0UD 65 Figure 4 7 Block Diagram of P23 and P24 Internal bus WRPU0 RD WRPORT WRPM PU02 Output latch P23 P24 PM23 PM24 VDD0 P ch P23 P24 Selector PU0 Pull up resistor option register 0 PM Port mode register RD Port 2 read signal WR Port 2 write signal ...

Page 66: ...ock Diagram of P25 RD VDD0 P25 WRPOM1 WRPU0 WRPORT WRPM Output latch P25 PM25 PU02 P ch P ch N ch VDD0 POM125 Internal bus Selector POM1 Port output mode register 1 PU0 Pull up resistor option register 0 PM Port mode register RD Port 2 read signal WR Port 2 write signal ...

Page 67: ...ock Diagram of P26 RD VDD0 P26 WRPOM1 WRPU0 WRPORT WRPM Output latch P26 PM26 PU02 P ch P ch N ch VDD0 POM126 Internal bus Selector POM1 Port output mode register 1 PU0 Pull up resistor option register 0 PM Port mode register RD Port 2 read signal WR Port 2 write signal ...

Page 68: ...put mode when the RESET signal is input Figure 4 10 shows a block diagram of port 4 Caution When using the pins of port 4 as the key return key return mode register 00 KRM00 must be set according to the function to be used For how to set the register see Section 11 3 5 Key return mode register 00 KRM00 Figure 4 10 Block Diagram of P40 to P47 WRKRM Internal bus VDD0 P40 KR00 to P47 KR07 WRPU0 RD WR...

Page 69: ... set the port mode register and output latch according to Table 4 3 Caution As P26 can be used as an external interrupt input when the port function output mode is specified and the output level is changed the interrupt request flag is set When the output mode is used therefore the interrupt mask flag should be set to 1 beforehand Figure 4 11 Format of Port Mode Register PMmn 0 Output mode output ...

Page 70: ...ster 0 PU0 The pull up resistor option register PU0 sets whether an on chip pull up resistor on each port is used or not On the port which is specified to use the on chip pull up resistor in the PU0 the pull up resistor can be internally used only for the bits set to the input mode No on chip pull up resistors can be used for the bits set in the output mode regardless of the setting PU0 This appli...

Page 71: ...output mode selectionNote m 0 1 0 0 0 0 0 POM01POM00 POM0 Address After reset R W FF30H 00H R W 7 6 5 4 3 2 1 0 POM0m 0 1 CMOS output N ch open drain output Symbol 0 Note POM0 selects the output mode for a port in 8 bit units Caution Bits 2 to 7 must be set to 0 Figure 4 14 Format of Port Output Mode Register 1 Output mode selection for bit n of port 2Note n 5 6 0 POM126 POM125 0 0 0 0 POM1 Addres...

Page 72: ...latch of the pin that is set to the input mode and not subject to manipulation become undefined 4 4 2 Reading from I O port 1 In output mode The status of a pin can be read by using a transfer instruction The contents of the output latch are not changed 2 In input mode The status of a pin can be read by using a transfer instruction The contents of the output latch are not changed 4 4 3 Arithmetic ...

Page 73: ...executing the STOP instruction 5 2 Clock Generator Configuration The clock generator consists of the following hardware Table 5 1 Configuration of Clock Generator Item Configuration Control register Processor clock control register PCC Oscillator System clock oscillator Figure 5 1 Block Diagram of Clock Generator Prescaler System clock oscillator fX Prescaler Standby controller Wait controller CPU...

Page 74: ... the of division ratio PCC is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets the PCC to 02H Figure 5 2 Format of Processor Clock Control Register CPU clock fCPU selection 0 0 0 0 0 0 PCC1 0 PCC Symbol Address After reset R W FFFBH 02H R W 7 6 5 4 3 2 1 0 PCC1 0 1 fX fX 22 µ µ Minimum instruction execution time 2 fCPU 0 33 s 1 33 s fX 6 0 MHz operation Caution Bits 0 and...

Page 75: ...lock Oscillator a Crystal oscillation b External clock Crystal resonator VSS0 X2 X1 External clock X1 X2 OPEN Caution When using the system clock oscillator wire as follows in the area enclosed by the broken lines in Figure 5 3 to avoid an adverse effect from wiring capacitance Keep the wiring length as short as possible Do not cross the wiring with other signal lines Do not route the wiring near ...

Page 76: ...sonator connection Figure 5 4 Examples of Incorrect Resonator Connection 1 2 a Too long wiring b Crossed signal line VSS0 X1 X2 VSS0 X1 X2 PORTn n 0 1 2 4 c Wiring near high fluctuating current VSS0 X1 X2 High current d Current flowing through ground line of oscillator potential at points A B and C fluctuates VSS0 X1 A B C Pmn VDD0 High current X2 ...

Page 77: ... The operation of the clock generator is determined by the processor clock control register PCC as follows a The slow mode 1 33 µs at 6 0 MHz operation of the system clock is selected when the RESET signal is generated PCC 02H While a low level is being input to the RESET pin oscillation of the system clock is stopped b Two types of minimum instruction execution time 0 33 µs and 1 33 µs at 6 0 MHz...

Page 78: ... 5 6 2 Switching CPU clock The following figure illustrates how the CPU clock switches Figure 5 5 Switching of CPU Clock VDD RESET CPU clock Slow operation Fastest operation Wait 5 46 ms at 6 0 MHz operation Internal reset operation 1 The CPU is reset when the RESET pin is made low on power application The effect of resetting is released when the RESET pin is later made high and the system clock s...

Page 79: ...as an interval timer it generates an interrupt at any preset time interval Table 6 1 Interval Time of 8 Bit Timer 00 Minimum Interval Time Maximum Interval Time Resolution 26 fX 10 7 µs 214 fX 2 73 ms 26 fX 10 7 µs 29 fX 85 3 µs 217 fX 21 8 ms 29 fX 85 3 µs Remarks 1 fX System clock oscillation frequency 2 The parenthesized values apply to operation at fX 6 0 MHz Table 6 2 Interval Time of 8 Bit T...

Page 80: ...MHz 6 2 Configuration of 8 Bit Timer Event Counters 00 and 01 8 bit timer event counters 00 and 01 consist of the following hardware Table 6 4 Configuration of 8 Bit Timer Event Counters 00 and 01 Item Configuration Timer counter 8 bits 2 TM00 and TM01 Register Compare register 8 bits 2 CR00 and CR01 Timer outputs 1 TO01 Control registers 8 bit timer mode control registers 00 and 01 TMC00 and TMC0...

Page 81: ...Selector 1 8 bit compare register 0n CR0n This is an 8 bit register used to compare the value set to CR0n with the 8 bit timer counter 0n TM0n count value and if they match generate used an interrupt request INTTM0n CR0n is set with an 8 bit memory manipulation instruction Values from 00H to FFH can be set RESET input sets CR0n undefined Caution Be sure to set CR0n after the timer operation is sto...

Page 82: ... set with a 1 bit or 8 bit memory manipulation instruction RESET input sets TMC00 to 00H Figure 6 3 Format of 8 Bit Timer Mode Control Register 00 TCE00 0 0 0 0 0 TCL000 0 TMC00 R W FF53H 00H R W 6 5 4 3 2 1 TCL000 0 0 TCE00 0 1 7 0 Operation enabled Symbol Address After reset 8 bit timer 00 count clock selection 8 bit timer counter 00 operation control Operation disabled TM00 cleared to 0 fX 26 9...

Page 83: ... FF57H 00H R W 6 7 5 4 3 2 1 0 TCL011 0 0 1 1 8 bit timer event counter 01 count clock selection TCL010 0 1 0 1 fX 24 fX 28 Rising edge of TI01Note Falling edge of TI01Note TCE01 0 1 8 bit timer counter 01 operation control Operation disabled TM01 is cleared to 0 Operation enabled 375 kHz 23 4 kHz TOE01 0 1 8 bit timer event counter 01 output control Output disabled port mode Output enabled Note W...

Page 84: ... output latch of P26 to 0 When P26 TO01 INTP0 TI01 pin is used as a timer input set PM26 to 1 PM2 is set by a 1 bit or 8 bit memory manipulation instruction RESET input sets PM2 to FFH Figure 6 5 Format of Port Mode Register 2 PM26 0 1 1 PM26 PM25 PM24 PM23 PM22 PM21 PM20 PM2 7 6 5 4 R W R W 3 2 1 0 Input mode output buffer off Symbol Address FF22H FFH After reset P26 pin input output mode selecti...

Page 85: ...res 6 6 and 6 7 show the timing of interval timer operation Caution When the TMC0n count clock is set and the operation of TM0n is enabled simultaneously by an 8 bit memory manipulation instruction an error of more than 1 clock may occur in 1 cycle after the timer has been started Therefore be sure to follow the settings above when the 8 bit timer event counter is operating as an interval timer Re...

Page 86: ...me Count clock TM00 count value CR00 TCE00 INTTM00 N 01 00 N 01 00 N 00 01 N N N N t Remark Interval time N 1 t where N 00H to FFH Figure 6 7 Interval Timer Operation Timing of 8 Bit Timer Event Counter 01 Clear Clear Interrupt acknowledged Interrupt acknowledged Count start Interval time Interval time Interval time Count clock TM01 count value CR01 TCE01 INTTM01 TO01 N 01 00 N 01 00 N 00 01 N N N...

Page 87: ...ied by bit 1 or 2 TCL011 or TCL010 of TMC01 is input the value of 8 bit timer counter 01 TM01 is incremented When the count value of TM01 matches the value set to CR01 the value of TM01 is cleared to 0 and TM01 continues counting At the same time an interrupt request signal INTTM01 is generated Figure 6 8 shows the timing of external event counter operation with rising edge specified Caution When ...

Page 88: ...P26 INTP0 TI01 pin output will be inverted Through application of this mechanism square waves of any frequency can be output As soon as a match occurs the TM01 value is cleared to 0 TM01 resumes counting and an interrupt request signal INTTM01 is generated Setting bit 7 of TMC01 TCE01 to 0 clears the square wave output to 0 Table 6 7 lists the square wave output range and Figure 6 9 shows timing o...

Page 89: ... Figure 6 9 Timing of Square Wave Output Clear Clear Interrupt acknowledged Interrupt acknowledged Count start Count clock TM01 count value CR01 TCE01 INTTM01 TO01Note N 01 00 N 01 00 N 00 01 N N N N Note The initial value of TO01 when output is enabled TOE01 1 becomes low level ...

Page 90: ...TM01 are started asynchronously to the count pulse Figure 6 10 Start Timing of 8 Bit Timer Counter Count pulse TM00 TM01 count value Timer starts 00H 01H 02H 03H 04H 2 Setting of 8 bit compare register 8 bit compare registers 00 and 01 CR00 and CR01 can be set to 00H Therefore one pulse can be counted when the 8 bit timer event counter operates as an event counter Figure 6 11 Timing of External Ev...

Page 91: ...tent loop is detected a non maskable interrupt or the RESET signal can be generated Table 7 1 Inadvertent Loop Detection Time of Watchdog Timer Inadvertent Loop Detection Time Operation at fX 6 0 MHz 211 1 fX 341 µs 213 1 fX 1 37 ms 215 1 fX 5 46 ms 217 1 fX 21 8 ms fX System clock oscillation frequency 2 Interval timer The interval timer generates an interrupt at arbitrary intervals set in advanc...

Page 92: ...egister Timer clock select register 2 TCL2 Watchdog timer mode register WDTM Figure 7 1 Block Diagram of Watchdog Timer Internal bus Internal bus Prescaler Selector Controller fX 26 fX 28 fX 210 3 7 bit counter Clear TMIF4 TMMK4 TCL22 TCL21 TCL20 Timer clock select register 2 TCL2 Watchdog timer mode register WDTM WDTM4 WDTM3 INTWDT maskable interrupt request RESET INTWDT non maskable interrupt re...

Page 93: ...anipulation instruction RESET input sets TCL2 to 00H Figure 7 2 Format of Timer Clock Select Register 2 TCL22 0 0 1 1 0 0 0 0 0 TCL22 TCL21 TCL20 TCL2 R W R W 7 6 5 4 3 2 1 0 TCL21 0 1 0 1 fX 24 fX 26 fX 28 fX 210 211 fX 213 fX 215 fX 217 fX TCL20 0 0 0 0 Settings prohibited Symbol Address FF42H 00H After reset Other than above Watchdog timer count clock selection Interval time 341 s 1 37 ms 5 46 ...

Page 94: ...nterrupt occur Note 3 Watchdog timer mode 1 overflow and non maskable interrupt occur Watchdog timer mode 2 overflow occurs and reset operation started 0 0 Notes 1 Once RUN has been set 1 it cannot be cleared 0 by software Therefore when counting is started it cannot be stopped by any means other than RESET input 2 Once WDTM3 and WDTM4 have been set 1 they cannot be cleared 0 by software 3 The wat...

Page 95: ... RUN to 1 the watchdog timer can be cleared and start counting If RUN is not set to 1 and the inadvertent loop detection time is exceeded the system is reset or a non maskable interrupt is generated by the value of bit 3 WDTM3 of WDTM The watchdog timer continues operation in the HALT mode but stops in the STOP mode Therefore set RUN to 1 before entering the STOP mode to clear the watchdog timer a...

Page 96: ...4 is valid and a maskable interrupt INTWDT can be generated The priority of INTWDT is set as the highest of all the maskable interrupts The interval timer continues operation in the HALT mode but stops in the STOP mode Therefore set RUN to 1 before entering the STOP mode to clear the interval timer and then execute the STOP instruction Cautions 1 Once bit 4 WDTM4 of WDTM is set to 1 when the watch...

Page 97: ...e 8 1 shows an example of USB connection to a desktop PC The USB consists of the host controller installed in the PC hubs installed for port expansion and connection and functions installed at bus ends These functions are called endpoints and are the data transfer destinations or data transfer sources in the USB Figure 8 1 USB Bus Topology Desktop Type PC Host Hub Hub RootHub Hub Hub Function moni...

Page 98: ...iguration Buffer Receive bank switching ID detection buffer internal buffer Registers Transmit receive pointer USBPOW Receive token PID USBRTP Receive token address L H USBRAL USBRAH Receive data PID USBRD Receive data address USBR0 to USBR7 Transmit data PID bank 0 USBTD0 Transmit data bank 0 address USBT00 to USBT07 Transmit data PID bank 1 USBTD1 Transmit data bank 1 address USBT10 to USBT17 Da...

Page 99: ...Note 4 7 bit counter USB timer start reservation control register USBTCL Receive result store registerNote 3 Packet receive status register RXSTAT CRC circuit ENDP detector Compare registerNote 2 Receive buffer Transmit buffer Bit stuff bit strip controller Receive bank switching ID detection buffer NRZI encoder Output latch Selector Notes 1 Data handshake packet receive byte number counter DRXCON...

Page 100: ...oller Shift register In high speed mode In low speed mode DATATX SETORX JUDGE TXNote JUDGE TOKENNote TX MASTER ENNote SETRXNote OUT RXNote USB timer start reservation control register USBTCL Note As these signals are used internally confirmation by software is not possible Remark fX System clock oscillation frequency UWDERR Bit 7 of packet receive status register RXSTAT ...

Page 101: ...an 8 bit memory manipulation instruction As USBPOB is an internal pointer control with software is not possible RESET input sets these pointers to 00H The value of USBPOW is changed as follows depending on the receive transmit byte length match signal or transmit reservation Moreover control signals are also output For details see Section 8 8 1 Operation of transmit receive pointer If the token pa...

Page 102: ...nd H USBRAL and USBRAH This stores the token packet to be transferred from the host USBRAL and USBRAH consist of 16 bits Bits 0 to 6 of USBRAL store the data input to the token address compare register ADRCMP Both USBRAL and USBRAH are read with an 8 bit memory manipulation instruction RESET input sets these registers to 00H Figure 8 4 Configuration of Receive Token Bank 00H 07H 06H 05H 04H 03H 02...

Page 103: ...ing combinations are used they are read with a 16 bit memory manipulation instruction USBR10 USBR0 and USBR1 USBR32 USBR2 and USBR3 USBR54 USBR4 and USBR5 USBR76 USBR6 and USBR7 RESET input makes USBR0 to USBR7 undefined Figure 8 5 Configuration of Receive Data Bank 10H 07H 06H 05H 04H 03H 02H 01H 00H 11H 12H 13H 14H 15H 16H 17H 18H USBRD USBR0 USBR1 USBR2 USBR3 USBR4 USBR5 USBR6 USBR7 USBPOW addr...

Page 104: ...ters that store the data to be transferred to the host USBT00 to USBT07 and USBT10 to USBT17 correspond to transmit buffer 0 of the data area and transmit buffer 1 of the data area respectively Because CRC redundant bits 16 bits are always appended to packets sent from these registers these registers cannot be used for transmitting handshake packets USBT00 to USBT07 and USBT10 to USBT17 are set wi...

Page 105: ...peration during transmission appears as follows 8th byte 1st byte USBT00 USBT07 USBT10 USBT17 IN DATA0 ACK Packet from host controller Response packet 8th byte 1st byte USBT00 USBT07 USBT10 USBT17 IN DATA1 ACK Data is read according to the data sequence in the control read data stage and is transmitted to the host In the DATA0 sequence the values saved in USBT00 to USBT07 are transmitted in sequen...

Page 106: ...ption 7 Data packet transmit byte number counters 0 and 1 DTXCO0 and DTXCO1 DTXCO0 sets the data packet data number of transmit data bank 0 and DTXCO1 sets the transmit data number of transmit data bank 1 During data packet transmission if these register values and the transmit receive pointer USBPOW value match a match signal is output from the comparator The value to be set to these registers is...

Page 107: ...ived ADRCMP is set with an 8 bit memory manipulation instruction RESET input sets ADRCMP to 00H Figure 8 8 Configuration of TIDCMP and ADRCMP 00H 07H 06H 05H 04H 03H 02H 01H 00H 01H 02H USBPOW address USBPOB address 0 0 1 0 1 1 0 1 0 1 1 0 1 0 0 1 1 1 1 0 0 0 0 1 ENDP 0 ENDP 3 1 Endpoint 0 detection signal END0RX Endpoint 1 detection signal END1RX Note Note Match signal TIDRST SETUP packet detecti...

Page 108: ...ndshake packet receive result store register DRXRSL is set DIDCMP is set with an 8 bit memory manipulation instruction RESET input sets DIDCMP to C3H SETUP reception Note also sets DIDCMP to C3H Note SETUP reception implies the satisfaction of all the following three conditions Matching of address Endpoint 0 received No error in reception Figure 8 9 Configuration of DIDCMP 00H 07H 06H 05H 04H 03H ...

Page 109: ...input sets USBMOD to 00H Figure 8 10 Format of USB Receiver Enable Register Symbol 6 7 5 4 3 2 1 0 0 0 0 0 0 0 0 RXEN RXEN USB receiver operation control 0 1 FF6DH Address USBMOD After reset 00H R W R W USB receiver operation is stopped USB receiver operation is possible 2 Data handshake packet receive mode register URXMOD This register sets the data handshake packet receive mode Bit 0 DWRMSK is s...

Page 110: ...ve buffer Disable write operation to addresses greater than 11H in data handshake packet receive buffer Note 1 Note 2 µ Notes 1 Because this is the flag used to detect a USB reset in bus suspend mode do not set data in bus idle mode And do not set data immediately before entering bus suspend mode Clear immediately when returning from the bus suspend mode 2 If the bus is disturbed by noise the nois...

Page 111: ...e flags that detect bus status transition These flags are set immediately after each bus transition is detected These flags are cleared by software but cannot be set to 1 by software Bit 7 UWDERR is set if an inadvertent program loop is detected by the USB timer The flags are cleared by software UWDERR cannot be set by software An inadvertent program loop of the USB timer means a status in which t...

Page 112: ...ignal receive status 0 1 No Resume signal was received Received Resume signal level detection SE0RX Single ended 0 signal detection status 0 1 No Single ended 0 SE0 signal was detected Detected SE0 signal one or more times URESRX USB reset signal detection status 0 1 No USB reset signal was detected Detected USB reset signal one or more times EOPRX EOP detection status 0 1 No EOP signal was detect...

Page 113: ...R DBITER DBYER 0 0 0 DIDRST 0 CR16ER CRC error detection 16 bit mode 0 1 FF65H Address DRXRSL After reset 00H R W R W CRC error did not occur in received data packet CRC error occurred in received data packet DBITER Bit stuffing error detection 0 1 Bit stuffing error did not occur in received data handshake packet Bit stuffing error occurred in received data handshake packet DBYER Received data ha...

Page 114: ...d Token packet corresponding to Endpoint 1 was received END0RX Endpoint 0 reception detection 0 1 No token packet corresponding to Endpoint 0 is received Token packet corresponding to Endpoint 0 was received ADRRST Token packet address compare result 0 1 Received token packet address and value of token address compare register ADRCMP do not match Received token packet address and value of ADRCMP m...

Page 115: ... R W No data is transmitted Stored data is transmitted when all the following conditions are satisfied in EOP during IN packet reception Setting is disabled during control read transmission INRX Internal signal 1 ADRRST 1 END1RX 1 TBYER 0 TBITER 0 CRC5ER 0 DT10EN Transmit reservation flag for transmit bank 1 Endpoint 0 0 1 No data is transmitted Stored data is transmitted when all the following co...

Page 116: ...E1NAEN E0NAEN DNAEN ACKEN E1STEN STALL packet transmit reservation flag for Endpoint 1 after IN packet 0 1 FF14H Address HTXRSV After reset 00H R W R W No data is transmitted STALL handshake is transmitted when all the following conditions are satisfied in EOP during IN packet reception INRX internal signal 1 ADRRST 1 END1RX 1 TBYER 0 TBITER 0 CRC5ER 0 E0STEN STALL packet transmit reservation flag...

Page 117: ...d in EOP during data packet reception Set this flag when saving data from reception data addresses USBR0 to USBR7 OUTRX internal signal 1 DIDRST 1 DBYER 0 DBITER 0 CR16ER 0 UWDERR 0 E1NAEN NAK packet transmit reservation flag for Endpoint 1 after IN packet 0 1 No data is transmitted NAK handshake is transmitted when all the following conditions are satisfied in EOP during IN packet reception INRX ...

Page 118: ...e reservations above Setting prohibited c Handshake transmit reservation for data packet Type of Reservation STALEN DNAEN STALL transmit reservation during occurrence of length error 1 0 NAK transmit reservation during previous receive data saveNote 0 1 Two or more reservations above Setting prohibited Type of Reservation ACKEN DNAEN ACK transmit reservation during normal data packet reception 1 0...

Page 119: ...Transmit Reservation Register END1RX END0RX TIDRST ADRRST DIDRST DBYER DBITER TBYER TBITER CRC5ER CR16ER JUDGE TOKENNote JUDGE DATANote TX MASTER ENNote E1STEN E1NAEN E0NAEN DNAEN ACKEN E0STEN DSTEN STALEN IN RXNote Note Because these signals are used internally confirmation by software is not possible ...

Page 120: ...in reception Figure 8 18 Format of USB Timer Start Reservation Control Register Symbol 6 7 5 4 3 2 1 0 0 0 0 0 0 0 DATATX SETORX DATATX USB timer start reservation after data packet transmission 0 1 FF6CH Address USBTCL After reset 01H R W R W Do not start USB timer USB timer starts when all the following conditions are satisfied in EOP during data packet transmission DIDRST 1 DBYER 0 DBITER 0 CR1...

Page 121: ...e Wakeup Control Register Symbol 6 7 5 4 3 2 1 0 0 0 0 0 PULLDM PULLDP PULLEN WAKEUP PULLDM D lead low high fixed output setting 0 1 FF6AH Address REMWUP After reset 08H R W R W D TXDM is fixed to low output D TXDM is fixed to high output PULLDP D lead low high fixed output setting 0 1 D TXDP is fixed to low output D TXDP is fixed to high output PULLEN D D lead fixed output enable 0 1 Output from ...

Page 122: ...P reception or data packet EOP transmission The start condition is set by the USB timer start reservation control register USBTCL Low speed mode is used for detecting inadvertent program loops of the USB clock The timer starts upon detection of the SYNC signal of a receive packet or upon reception of the USB reset or Resume signals When the USB timer overflows an interrupt request signal INTUSBTM ...

Page 123: ...ransmit data transferring Transmit EOP is output DATA TX internal signal 1 Idle state USB timer reset USB timer start low speed mode USB timer reset 3 IN packet INTUSBTM occurred UWDERR set inadvertent program loop detection Low speed mode overflow 1 2 Y Y Y Y N N N N Y Y SETUP OUT packet N N N N N Y Y Y UWDERR Bit 7 of packet receive status register RXSTAT ...

Page 124: ...ER 8 USB FUNCTION User s Manual U12978EJ3V0UD 124 Figure 8 20 Flowchart of USB Timer Operation 2 2 2 INTUSBTM occurred High speed mode overflow 3 N Y N Y 1 Next SYNC detected USB timer start high speed mode ...

Page 125: ...1 PULLDP 0 PULLDM 1 PULLDP 0 PULLDM 1 PULLEN 0 PULLDP 0 PULLDM 1 Resume outputNote 1 WAKEUP 0 Idle state Y N Is bus idle duration longer than 5 ms REMWUP A Did HOST output USB reset or Resume Idle state Resume output completionNote 2 PULLDP Bit 2 of remote wakeup control register REMWUP PULLDM Bit 3 of remote wakeup control register REMWUP PULLEN Bit 1 of remote wakeup control register REMWUP WAKE...

Page 126: ...ct instruction sequence to append EOP when terminating Resume output CLR1 REMWUP 0 WAKEUP 0 Resume output end CLR1 REMWUP 1 PULLEN 0 CLR1 REMWUP 2 PULLDP 0 SET1 REMWUP 3 PULLDM 1 Figure 8 22 Configuration of Remote Wakeup Control TXENNote WAKEUP REMWUP 0 PULLDP REMWUP 2 Transmit data side Transmit data side PULLDM REMWUP 3 PULLEN REMWUP 1 Analog part Function part D pin USBDP D pin USBDM SEP SEM d...

Page 127: ...ection during token packet reception an interrupt request signal is generated and an interrupt request flag USBRTIF is set If ADRRST bit 2 of the token packet receive result store register TRXRSL is 0 no interrupt request is generated because a token packet of another device exists on the bus 2 Data handshake packet receive interrupt INTUSBRD Upon EOP detection during data handshake packet recepti...

Page 128: ...0 to K state logic 1 is detected on the bus or transition to SE0 is detected an interrupt request signal is generated and an interrupt request flag USBREIF is set Figure 8 24 Timing of INTUSBRE Generation a Period of RESMOD 0 and Single ended 0 SE0 is 3 0 µ µ µ µs or longer microcontroller operation D USBDP D USBDM INTUSBRE L 3 0 s or longer 3 0 s µ µ b Period of RESMOD 0 and SE0 is shorter than 3...

Page 129: ...SE0 state on the bus it is also set during EOP reception or bus idle retention EOP reception Thus disable the generation of interrupt requests by setting the interrupt mask flag USBREMK during bus idle or control transfer 3 When clearing the interrupt mask flag USBREMK do so immediately before the transition to bus suspend mode immediately before the STOP instruction execution 4 When the USB reset...

Page 130: ...on of host controller OUT packet SETUP DATA0 ACK Packet from host controller Packet from PD789800 Setup stage Data stage OUT reception IN ACK OUT DATA1 DATA1 ACK ACK transmission NAK transmission reservation Operation of USB function of PD789800 ACK transmission reservation NAK transmission reservation clear ACK transmission reservation ACK transmission DATA1 transmission reservation IN packet DAT...

Page 131: ...sion reservation clear ACK transmission reservation ACK transmission DATA1 transmission reservation IN packet DATA1 transmission NAK transmission reservation Status stage IN reception Packet flow ACK packet ACK OUT DATA0 ACK OUT DATA1 OUT packet ACK transmission NAK transmission reservation NAK transmission reservation clear ACK transmission reservation OUT packet ACK transmission NAK transmission...

Page 132: ... reservation DATA1 transmission NAK transmission reservation ACK transmission USB communication completion timer start NAK transmission reservation OUT reception wait Status stage OUT reception Packet flow ACK OUT packet NAK transmission reservation clear OUT DATA1 ACK transmission reservation USB communication completion timer timeoutNote µ µ Note If the ACK from the device cannot be received nor...

Page 133: ...ervation OUT reception wait Status stage OUT reception Packet flow ACK packet ACK IN DATA0 ACK IN packet NAK transmission reservation clear NAK transmission DATA0 transmission reservation ACK packet DATA0 transmission NAK transmission reservation NAK transmission reservation clear OUT DATA1 OUT packet DATA0 1 transmission NAK transmission reservation ACK transmission reservation NAK IN IN DATA0 1 ...

Page 134: ...packet SETUP DATA0 ACK Packet from host controller Packet from PD789800 Setup stage Status stage No data control IN DATA1 ACK transmission DATA1 transmission reservation Operation of USB function of PD789800 ACK transmission reservation DATA1 transmission Packet flow ACK ACK packet NAK transmission reservation µ µ ...

Page 135: ...ion DATA1 transmission reservation Operation of USB function of PD789800 ACK transmission reservation DATA1 transmission NAK transmission reservation Packet flow ACK IN packet NAK transmission reservation clear ACK IN IN packet IN NAK IN DATA0 NAK transmission DATA0 transmission reservation DATA0 transmission NAK transmission reservation IN packet NAK transmission NAK transmission reservation µ µ ...

Page 136: ...1 Receive token is SETUP Receive token is unplanned token IN token reception to ENDPOINT 1 IN token reception processing to ENDPOINT 0 OUT token reception processing when status stage IN or data stage IN is received IN token reception processing to ENDPOINT 1 OUT token reception processing to ENDPOINT 1 OUT token reception processing Token mismatch processing SETUP token reception processing Yes Y...

Page 137: ... was received USB_MODE is SETUP USB_MODE is data stage OUT reception Re transmit data reception reservation processing Transition processing to status stage OUT reception USB request processing USB_MODE is waiting for communication request ACK reception processing to ENDPOINT 1 DATA ACK reception processing to ENDPOINT 0 Yes Yes Yes No No No No Yes ...

Page 138: ... Manual U12978EJ3V0UD 138 3 USB timer inadvertent program loop detection interrupt servicing INTUSBTM occurrence RETI Processing for each operation mode when ACK is not received and for when DATA is not received after receiving OUT ...

Page 139: ...andby detected Communication operating RESET received Waiting for resume signal completion RESUME output processing USB reset processing Resume signal completion wait processing Yes Yes Yes Yes No No No No No Yes Standby processing USB communication completion timer processing 10 ms timer counting DURATION base timer processing ...

Page 140: ...POW to 00H USBPOB increment USBPOW increment Set USBPOB to 00H Transmit receive signal Does bit stuffing signal 1 USBPOB overflow USBPOW 01H USBPOW 02H USBPOB 02H Bit normal write USBPOB increment Set USBPOW to 70H Set USBPOB to 00H Does bit stuffing signal 1 Does bit stuffing signal 1 Bit normal write Bit normal write Token reception Set TBYER flag Set CRC5 execution start signal Idle state Set T...

Page 141: ...eive Pointer Operation 2 7 1 Token packet reception 2 2 Y Y Y EOP Y N N N 2 USBPOW 05H USBPOB increment Idle state Does bit stuffing signal 1 Bit normal write EOP normal receive Set TBYER flag Idle state Set TBYER flag Idle state TBYER Bit 5 of token packet receive result store register TRXRSL ...

Page 142: ...B to 00H Transmit receive signal USBPOB overflow USBPOW 11H Does bit stuffing signal 1 USBPOB overflow Does USBPOW match DRXCON USBPOB increment Set USBPOW to 70H Does bit stuffing signal 1 Bit normal write Bit normal write HSSTAT 1 Data handshake reception Set DBYER flag Set CRC16 execution start signal Idle state Set DBYER flag Idle state Y DBYER Bit 5 of data handshake packet receive result sto...

Page 143: ...hake packet reception 2 2 Y Y Y EOP Y N N N N 2 1 USBPOB overflow Y USBPOW 71H USBPOB increment USBPOW increment USBPOB increment Idle state Does bit stuffing signal 1 Bit normal write EOP received normally Set DBYER flag Idle state Set DBYER flag Idle state DBYER Bit 5 of data handshake packet receive result store register DRXRSL ...

Page 144: ... n0H Set USBPOB to 00H Bit read Transmit receive signal Does bit stuffing signal 1 USBPOB overflow USBPOW n1H Transmit area reservation flag judgment USBPOB overflow USBPOB increment USBPOW increment Bit Read Does bit stuffing signal 1 Does USBPOW match DTXCOm Data handshake transmission Set CRC16 execution start signal Go to 4 n 2 Transmit buffer 0 n 3 Transmit buffer 1 m 0 send buffer 0 m 1 send...

Page 145: ...nter Operation 6 7 3 Data packet transmit 2 2 Y Y N N N 2 3 3 USBPOB overflow Y N USBPOB overflow Y USBPOW 71H USBPOB increment USBPOB increment USBPOW increment Bit Read Set USBPOW to 70H Read CRC redundant bit Does bit stuff signal 1 Y N Does bit stuffing signal 1 Set EOP transmit signal Idle state ...

Page 146: ... Y N N 1 Y Y N N 1 Idle state Set USBPOW to 7FH USBPOB increment Set USBPOW to n0H Set USBPOB to 00H Bit read Transmit receive signal Does bit stuffing signal 1 USBPOB overflow Transmit area reservation flag judgment USBPOB overflow Bit read USBPOB increment Set EOP transmit signal Idle state Does bit stuffing signal 1 Data handshake transmission Go to 3 n 4 ACK n 5 NAK n 6 STALL ...

Page 147: ...ration Y Y Y 01B 00B N Idle state Idle state 2 bit store shift 1 bit store shift Set buffer to 00H Bit judgment enable Set TOSTAT Bit judgment mask Sync1 detection signal 1 EOP received Store bit Set DASTAT Set HSSTAT 11B 10B TOSTAT Bit 0 of packet receive status register RXSTAT DASTAT Bit 1 of packet receive status register RXSTAT HSSTAT Bit 2 of packet receive status register RXSTAT ...

Page 148: ...tput Figure 8 27 Timing of Sync Detection USBCLK Detector Operation Receive packet USBCLK USBCLK generation NRZI decode Data after decoding SYNC last bit detection SYNC pattern After token packet Figure 8 28 Timing of Sync Detection USBCLK Generation Operation fX USBCLK Receive data RXD Resume RXNote INTUSBRE TX MASTER ENNote Sync Idle L 1 0 1 0 1 0 1 1 1 0 0 Note Because these signals are used in...

Page 149: ...Idle state USB clock oscillation start Detect last Sync bit Receive next bit Receive next bit Output 0 from NRZI decoder Output 0 from NRZI decoder Output 1 from NRZI decoder Output 1 from NRZI decoder Did state change to K state Was EOP receive signal set Did bus state change Did bus state change USB clock stop Idle state Sync detection ...

Page 150: ... Encoder Operation Data before encoding USB clock generation NRZI encoding Transmit packet Sync pattern Data handshake packet Figure 8 31 Flow Chart of NRZI Encoder Operation Y Y Y N N Idle state Idle state Sync 0 input Next bit input Reverse output level Reverse output level 1 output Transmit start Input bit 0 Was EOP transmit signal set Maintain previous output level N ...

Page 151: ...bit that should be deleted was a logic 1 this is detected as a bit stuffing error Figure 8 32 Timing of Bit Stuffing Strip Controller Operation 1 Bit stuffing If 1 occurs six successive times a 0 is inserted forcibly to shift the level Idle NRZI encoding data Sync pattern Packet data Idle Bit stuffing data Sync pattern Packet data Idle RAW data Sync pattern Packet data Logic 1 6 times Stuff bit 2 ...

Page 152: ...rol Operation Y Y Y N N Idle state Idle state Transmit bit input Shift bit stuffing register Disable save of next transmit bit Reset bit stuffing register Disable USBPOB increment Transmission start Transmit bit 1 Y N Bit stuffing register 3FH Was EOP receive signal set Reset bit stuffing register N ...

Page 153: ...ate Idle state Receive bit input Shift bit stuffing register Receive bit input Bit stuffing error output Disable USBPOB increment Reception start Receive bit 1 N Y Y N Bit stuffing register 3FH Was EOP receive signal set Was EOP receive signal set Reset bit stuffing register Y N Receive bit 1 Reset bit stuffing register N 1 1 ...

Page 154: ... transfer is carried out with three lines one for the serial clock SCK10 and two for serial data SI10 and SO10 The 3 wire serial I O mode supports simultaneous transmit and receive operations reducing data transfer processing time It is possible to switch the start bit of 8 bit data to be transmitted between the MSB and the LSB thus allowing connection to devices with either start bit The 3 wire s...

Page 155: ...onfiguration Register Transmit receive shift register 10 SIO10 Control register Serial operating mode register 10 CSIM10 1 Transmit receive shift register 10 SIO10 This is an 8 bit register used for parallel to serial conversion and to perform serial data transmission reception in synchronization with the serial clock SIO10 is set with an 8 bit memory manipulation instruction RESET input makes SIO...

Page 156: ...ram of Serial Interface 10 Internal bus CSIE10 TPS100 DIR10 Serial operation mode register 10 CSIM10 CSCK10 Transmit receive shift register 10 SIO10 Serial clock counter Clock controller F F Interrupt request generator Selector Selector SI10 P22 SO10 P21 SCK10 P20 fX 22 fX 23 INTCSI10 ...

Page 157: ...on instruction RESET input sets CSIM10 to 00H Figure 9 2 Format of Serial Operation Mode Register 10 CSIE10 0 1 Operation control in 3 wire serial I O mode CSIE10 0 0 TPS100 0 DIR10 CSCK10 0 CSIM10 Symbol Address After reset R W FF72H 00H R W 7 6 5 4 3 2 1 0 Operation disabled Operation enabled TPS100 0 1 Count clock selection when operation enabled in 3 wire serial I O mode fX 22 fX 23 DIR10 0 1 ...

Page 158: ...an above Setting prohibited 2 3 wired serial I O mode CSIM10 PM22 P22 PM21 P21 PM20 P20 Start Shift P22 SI10 P21 SO10 P20 SCK10 CSIE10 DIR10 CSCK10 Bit Clock Pin Function Pin Function Pin Function 1 0 0 1Note 2 Note 2 0 1 1 MSB External clock SI10Note 2 SO10 CMOS output SCK10 input 1 0 1 Internal clock SCK10 output 1 1 0 1 LSB External clock SCK10 input 1 0 1 Internal clock SCK10 output Other than...

Page 159: ...20 SCK10 P21 SO10 and P22 SI10 pins can be used as normal I O ports 1 Register setting Operation stop mode is set by serial operation mode register 10 CSIM10 Serial operation mode register 10 CSIM10 CSIM10 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets CSIM10 to 00H CSIE10 0 1 Operation control in 3 wire serial I O mode CSIE10 0 0 TPS100 0 DIR10 CSCK10 0 CSIM10 Symbo...

Page 160: ... serial operating mode register 10 CSIM10 a Serial operation mode register 10 CSIM10 CSIM10 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets CSIM10 to 00H CSIE10 0 1 Operation control in 3 wire serial I O mode CSIE10 0 0 TPS100 0 DIR10 CSCK10 0 CSIM10 Symbol Address After reset R W FF72H 00H R W 7 6 5 4 3 2 1 0 Operation disabled Operation enabled TPS100 0 1 Count cloc...

Page 161: ...SI10 Cautions 1 When data is written to SIO10 in the serial operation disabled status CSIE10 0 the data cannot be transmitted or received 2 When data is written to SIO10 in the serial operation disabled status CSIE10 0 and then serial operation is enabled CSIE10 1 the data cannot be transmitted or received 3 Once data has been written to SIO10 with the serial clock selected CSCK10 0 overwriting th...

Page 162: ...pin Supports power saving mode reducing power consumption in mode Figure 10 1 Block Diagram of Regulator and USB Driver Receiver Regulator PD789800 RXD USB driver receiver SEP SEM TXDP TXDM TXEN RXEN VDD0 VSS0 VSS VREG VDD0 VSS0 USBDM Hub REGC 22 F 1 5 kΩ USBDP µ µ Cautions 1 To stabilize the VREG voltage connect the REGC pin to VSS via 22 µ µ µ µF capacitor 2 Connect the pull up resistor 1 5 kΩ Ω...

Page 163: ... One interrupt source from the watchdog timer is incorporated as a non maskable interrupt 2 Maskable interrupt These interrupts undergo mask control If two or more interrupts with the same priority are simultaneously generated each interrupt has a predetermined priority as shown in Table 11 1 A standby release signal is generated Two external and nine internal interrupt sources are incorporated as...

Page 164: ...n from J state to K state or SE0 on the USB bus 000EH 6 INTP0 Detection of a pin input edge External 0010H C 7 INTCSI10 End of three wire SIO bus interface transmission and reception Internal 0012H B 8 INTTM00 Generation of the 8 bit timer 00 match signal 0014H 9 INTTM01 Generation of the 8 bit timer event counter 01 match signal 0016H 10 INTKR00 Detection of the key return signal External 0018H C...

Page 165: ... signal B Internal maskable interrupt MK IF IE Internal bus Interrupt request Vector table address generator Standby release signal C External maskable interrupt MK IF IE Internal bus INTM0 KRM00 Interrupt request Edge detector Vector table address generator Standby release signal IF Interrupt request flag IE Interrupt enable flag MK Interrupt mask flag INTM0 External interrupt mode register 0 KRM...

Page 166: ...ord PSW Key return mode register 00 KRM00 Table 11 2 gives a listing of interrupt request flag and interrupt mask flag names corresponding to interrupt requests Table 11 2 Flags Corresponding to Interrupt Request Signals Interrupt Request Signal Name Interrupt Request Flag Interrupt Mask Flag INTWDT TMIF4 TMMK4 INTUSBTM USBTMIF USBTMMK INTUSBRT USBRTIF USBRTMK INTUSBRD USBRDIF USBRDMK INTUSBST USB...

Page 167: ...d Interrupt request signal is generated interrupt request state XXIFX TMIF01 TMIF00 CSIIF10 KRIF00 0 0 PIF0 TMIF4 IF0 R W FFE0H 00H R W 0 USBTMIFUSBRTIFUSBRDIFUSBSTIF USBREIF 0 0 Symbol Address After reset 6 5 4 3 2 1 7 0 6 5 4 3 2 1 7 0 Cautions 1 The TMIF4 flag is R W enabled only when the watchdog timer is used as an interval timer If watchdog timer mode 1 or 2 is used set the TMIF4 flag to 0 2...

Page 168: ...n alternate function as an external interrupt input when the output level is changed by specifying the output mode of the port function an interrupt request flag is set Therefore the interrupt mask flag should be set to 1 before using the output mode 3 External interrupt mode register 0 INTM0 This register is used to set the valid edge of INTP0 INTM0 is set with an 8 bit memory manipulation instru...

Page 169: ... 8 bit unit read write this register can carry out operations with bit manipulation instructions and dedicated instructions EI DI When a vectored interrupt is acknowledged the PSW is automatically saved into a stack and the IE flag is reset to 0 RESET input sets the PSW to 02H Figure 11 5 Configuration of Program Status Word IE Z 0 AC 0 0 1 CY PSW 7 6 5 4 3 2 1 0 IE 0 1 02H Symbol After reset Used...

Page 170: ...KR0n KRM00n 0 1 Key return signal detection selection for P40 KR00 to P43 KR03 pins No detection Detection detecting falling edge of P40 KR00 to P43 KR03 KRM000 KRM007 KRM006 KRM005 KRM004 0 0 0 KRM000 KRM00 R W FFF5H 00H R W Symbol Address After reset 6 5 4 3 2 1 7 0 Cautions 1 Bits 1 to 3 must be set to 0 2 When the KRM00 register is set to 1 a pull up resistor is connected automatically However...

Page 171: ...l and takes precedence over all other interrupts When the non maskable interrupt request is acknowledged the PSW and PC are saved to the stack in that order the IE flag is reset to 0 the contents of the vector table are loaded to the PC and then program execution branches Caution During non maskable interrupt service program execution do not input another non maskable interrupt request if it is in...

Page 172: ...d Interrupt servicing is started WDTM3 0 non maskable interrupt is selected WDTM Watchdog timer mode register WDT Watchdog timer Figure 11 9 Timing of Non Maskable Interrupt Request Acknowledgment Instruction Instruction Save PSW and PC and jump to interrupt servicing Interrupt servicing program CPU processing TMIF4 Figure 11 10 Acknowledging Non Maskable Interrupt Request Second interrupt servici...

Page 173: ...y before a BT or BF instruction Remark 1 clock fCPU CPU clock When two or more maskable interrupt requests are generated at the same time they are acknowledged starting from the one assigned the highest priority A pending interrupt is acknowledged when the status in which it can be acknowledged is set Figure 11 11 shows the algorithm of acknowledging interrupts When a maskable interrupt request is...

Page 174: ... is acknowledged after MOV A r has been executed Figure 11 13 Timing of Interrupt Request Acknowledgment When Interrupt Request Flag Is Generated at Last Clock of Instruction Execution Clock CPU NOP MOV A r Save PSW and PC and jump to interrupt servicing Interrupt servicing program Interrupt 8 clocks When an interrupt request flag xxIF is generated at the last clock for instruction execution after...

Page 175: ...pt servicing Multiplexed interrupt is not performed unless interrupt requests are enabled IE 1 except the non maskable interrupt request Other interrupt requests are disabled IE 0 as soon as an interrupt request is acknowledged Therefore it is necessary to set 1 the IE flag to realize the interrupt enable state using the EI instruction during interrupt request servicing in order to enable multiple...

Page 176: ...interrupt is acknowledged the IE instruction is issued and interrupt requests are enabled Example 2 Multiplexed interrupts are not performed because interrupts are disabled INTyy EI Main processing RETI INTyy processing INTxx processing IE 0 INTxx RETI INTyy is held pending IE 0 Interrupt requests are disabled EI instruction is not issued in the interrupt INTxx servicing The interrupt request INTy...

Page 177: ...rnal interrupt is requested when a certain type of instruction is being executed the interrupt request will not be acknowledged until the instruction is completed Such instructions include Instructions that manipulate interrupt request flag registers 0 and 1 IF0 and IF1 Instructions that manipulate interrupt mask flag registers 0 and 1 MK0 and MK1 ...

Page 178: ... instruction is executed The STOP mode stops the system clock oscillator and stops the entire system The power consumption of the CPU can be substantially reduced in this mode The STOP mode can be released by an interrupt request so that this mode can be used for intermittent operations However some time is required until the system clock oscillator stabilizes after the STOP mode has been released...

Page 179: ...illation Stabilization Time Select Register OSTS2 0 0 1 0 0 0 0 0 OSTS2 OSTS1 OSTS0 OSTS R W FFFAH 04H R W 7 6 5 4 3 2 1 0 OSTS1 0 1 0 212 fX 215 fX 217 fX 683 s 5 46 ms 21 8 ms OSTS0 0 0 0 Setting prohibited Symbol Address After reset Oscillation stabilization time selection Other than above µ Caution The wait time after the STOP mode is released does not include the time from STOP mode release t...

Page 180: ...ock generator Oscillation enabled CPU Operation disabled Port output latch Remains in the state before the selection of HALT mode 8 bit timer 00 TM00 Operation enabled 8 bit timer event counter 01 TM01 Operation enabled Watchdog timer Operation enabled USB function Operation enabled Serial interface Operation enabled Key return Operation enabledNote 1 External interrupt Operation enabledNote 2 Not...

Page 181: ...cuted Figure 12 2 Releasing HALT Mode by Interrupt HALT instruction Standby release signal Wait Wait HALT mode Operation mode Operation mode Clock Oscillation Remarks 1 The broken lines indicate the case where the interrupt request that has released the standby mode is acknowledged 2 The wait time is as follows When vectored interrupt servicing is performed 9 to 10 clocks When vectored interrupt s...

Page 182: ...X 5 46 ms Reset period HALT mode Operation mode Oscillation stabilization wait status Clock Operation mode Oscillation stops Oscillation Oscillation Remarks 1 fX System clock oscillation frequency 2 The parenthesized values apply to operation at fX 6 0 MHz Table 12 2 Operation After Release of HALT Mode Releasing Source MKxx IE Operation Maskable interrupt request 0 0 Executes next address instruc...

Page 183: ...illation stabilization time select register OSTS elapses and then the operation mode is set The operation status in the STOP mode is shown in the following table Table 12 3 STOP Mode Operation Status Item STOP Mode Operation Status Clock generator Oscillation disabled CPU Operation disabled Port output latch Remains in the state before the selection of STOP mode 8 bit timer 00 TM00 Operation disab...

Page 184: ...pt servicing is performed after the oscillation stabilization time has elapsed If interrupt acknowledgement is disabled the instruction at the next address is executed Figure 12 4 Releasing STOP Mode by Interrupt STOP instruction Standby release signal Wait set time by OSTS STOP mode Operation mode Oscillation stabilization wait status Clock Operation mode Oscillation stops Oscillation Oscillation...

Page 185: ...ecutes next address instruction 0 1 Executes interrupt servicing 1 Retains STOP mode RESET input Reset processing don t care 3 Cautions an executing STOP instruction After the STOP instruction is executed in the SE0 state USBDM 0 USBDP 0 the STOP mode cannot be released by a USB reset Resume detection interrupt INTUSBRE Therefore the following control should be performed Control method Do not exec...

Page 186: ...ring the oscillation stabilization time just after reset release When a high level is input to the RESET pin the reset is released and program execution is started after the oscillation stabilization time 2 15 fx has elapsed The reset applied by watchdog timer overflow is automatically released after reset and program execution is started after the oscillation stabilization time 2 15 fx has elapse...

Page 187: ...Overflow in Watchdog Timer X1 Overflow in watchdog timer Internal reset signal Port pin Hi Z During normal operation Reset period oscillation stops Normal operation reset processing Oscillation stabilization time wait Figure 13 4 Reset Timing by RESET Input in STOP Mode X1 RESET Internal reset signal Port pin Delay Delay Hi Z STOP instruction execution During normal operation Reset period oscillat...

Page 188: ...er event counter Timer counter TM00 TM01 00H Compare register CR00 CR01 Undefined Mode control register TMC00 TMC01 00H Watchdog timer Timer clock select register TCL2 00H Mode register WDTM 00H USB function Transmit receive pointer USBPOW 00H Receive token PID USBRTP 00H Receive token address USBRAL USBRAH 00H Receive data PID USBRD 00H Receive data address USBR0 to USBR7 Undefined Transmit data ...

Page 189: ...ata handshake packet receive result store register DRXRSL 00H Token packet receive result store register TRXRSL 00H Data handshake PID compare register DIDCMP C3H Data packet transmit reservation register DTXRSV 00H Handshake packet transmit reservation register HTXRSV 00H USB timer start reservation control register USBTCL 01H Remote wakeup control register REMWUP 08H Serial interface Mode regist...

Page 190: ...78F9801 µPD789800 Internal memory ROM 16 KB Flash memory 8 KB High speed RAM 256 bytes IC pin Not provided Provided VPP pin Provided Not provided Electrical specifications Refer to CHAPTER 16 ELECTRICAL SPECIFICATIONS Caution There are differences in noise immunity and noise radiation between the flash memory and mask ROM versions When pre producing an application set with the flash memory version...

Page 191: ...rocontroller is solder mounted on the target system Distinguishing software facilities small quantity varied model production Easy data adjustment when starting mass production 14 1 1 Programming environment The following shows the environment required for µPD78F9801 flash memory programming When Flashpro III part no FL PR3 PG FP3 or Flashpro IV part no FL PR4 PG FP4 is used as a dedicated flash p...

Page 192: ...re sync 100 Hz to 1 25 MHzNote 2 Optional 1 to 5 MHzNote 2 1 0 SI10 P22 SO10 P21 SCK10 P20 0 Pseudo 3 wire Port A pseudo 3 wire 100 Hz to 1 kHz Optional 1 to 5 MHzNote 2 1 0 P10 serial clock input P11 serial data output P12 serial data input 12 Notes 1 Selection items for TYPE settings on the dedicated flash programmer Flashpro III part no FL PR3 PG FP3 Flashpro IV part no FL PR4 PG FP4 2 The poss...

Page 193: ...rammer VPP1 VDD RESET SCK SO SI GND VPP VDD0 VDD1 RESET P10 P12 P11 CLKNote X1 VSS0 VSS1 PD78F9801 µ Note Connect this pin when the system clock is supplied from the dedicated flash programmer If a resonator is already connected to the X1 pin the CLK pin does not need to be connected Caution The VDD pin if already connected to the power supply must be connected to the VDD pin of the dedicated flas...

Page 194: ...rial I O Pseudo 3 Wire VPP1 Output Write voltage VPP VPP2 VDD I O VDD voltage generation voltage monitoring VDD0 VDD1 Note Note GND Ground VSS0 VSS1 CLK Output Clock output X1 RESET Output Reset signal RESET SI Input Receive signal SO10 P11 SO Output Transmit signal SI10 P12 SCK Output Transfer clock SCK10 P10 HS Input Handshake signal Note VDD voltage must be supplied before programming is starte...

Page 195: ...following 1 Connect a pull down resistor RVPP 10 kΩ to the VPP pin 2 Use the jumper on the board to switch the VPP pin input to either the writer or directly to GND A VPP pin connection example is shown below Figure 14 4 VPP Pin Connection Example PD78F9801 VPP Connection pin of dedicated flash programmer Pull down resistor RVPP µ Serial interface pin The following shows the pins used by the seria...

Page 196: ...normal operation of other device If the dedicated flash programmer output or input is connected to a serial interface pin input or output that is connected to another device input a signal is output to the device and this may cause an abnormal operation To prevent this abnormal operation isolate the connection with the other device or set so that the input signals to the other device are ignored F...

Page 197: ... the µPD78F9801 enters the flash memory programming mode all the pins other than those that communicate with flash programmer are in the same status as immediately after reset If the external device does not recognize initial statuses such as the output high impedance status therefore connect the external device to VDD0 VDD1 VSS0 or VSS1 via a resistor Resonator When using the on board clock conne...

Page 198: ...onnection when the adapter for flash writing is used Figure 14 8 Wiring Example for Flash Writing Adapter with 3 Wire Serial I O 12 13 14 15 16 17 18 19 20 21 22 23 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 PD78F9801 GND VDD SI SO SCK CLKOUT RESET VPP RESERVE HS VDD 4 0 to 5 5 V GND VDD2 LVDD 44 43 42 41 40 39 38 37 36 35 34 WRITER INTERFACE FRASH µ ...

Page 199: ... for Flash Writing Adapter with Pseudo 3 Wire Method 12 13 14 15 16 17 18 19 20 21 22 23 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 PD78F9801 GND VDD SI SO SCK CLKOUT RESET VPP RESERVE HS VDD 4 0 to 5 5 V GND VDD2 LVDD 44 43 42 41 40 39 38 37 36 35 34 WRITER INTERFACE FRASH µ ...

Page 200: ...rect address specification In the case of immediate data describe an appropriate numeric value or a label When using a label be sure to describe the and symbols For operand register identifiers r and rp either function names X A C etc or absolute names names in parentheses in the table below R0 R1 R2 etc can be used for description Table 15 1 Operand Identifiers and Description Methods Identifier ...

Page 201: ... AC Auxiliary carry flag Z Zero flag IE Interrupt request enable flag NMIS Flag indicating non maskable interrupt servicing in progress Memory contents indicated by address or register contents in parenthesis xH xL Higher 8 bits and lower 8 bits of 16 bit register Logical product AND Logical sum OR V Exclusive logical sum exclusive OR Inverted data addr16 16 bit immediate data or label jdisp8 Sign...

Page 202: ...sfr sfr A 2 4 sfr A A addr16 3 8 A addr16 addr16 A 3 8 addr16 A PSW byte 3 6 PSW byte A PSW 2 4 A PSW PSW A 2 4 PSW A A DE 1 6 A DE DE A 1 6 DE A A HL 1 6 A HL HL A 1 6 HL A A HL byte 2 6 A HL byte HL byte A 2 6 HL byte A XCH A X 1 4 A X A rNote 2 2 6 A r A saddr 2 6 A saddr A sfr 2 6 A sfr A DE 1 8 A DE A HL 1 8 A HL A HL byte 2 8 A HL byte Notes 1 Except r A 2 Except r A X Remark One instruction...

Page 203: ...dr16 A HL 1 6 A CY A HL A HL byte 2 6 A CY A HL byte ADDC A byte 2 4 A CY A byte CY saddr byte 3 6 saddr CY saddr byte CY A r 2 4 A CY A r CY A saddr 2 4 A CY A saddr CY A addr16 3 8 A CY A addr16 CY A HL 1 6 A CY A HL CY A HL byte 2 6 A CY A HL byte CY SUB A byte 2 4 A CY A byte saddr byte 3 6 saddr CY saddr byte A r 2 4 A CY A r A saddr 2 4 A CY A saddr A addr16 3 8 A CY A addr16 A HL 1 6 A CY A...

Page 204: ...saddr saddr byte A r 2 4 A A r A saddr 2 4 A A saddr A addr16 3 8 A A addr16 A HL 1 6 A A HL A HL byte 2 6 A A HL byte OR A byte 2 4 A A byte saddr byte 3 6 saddr saddr byte A r 2 4 A A r A saddr 2 4 A A saddr A addr16 3 8 A A addr16 A HL 1 6 A A HL A HL byte 2 6 A A HL byte XOR A byte 2 4 A AVbyte saddr byte 3 6 saddr saddr Vbyte A r 2 4 A AVr A saddr 2 4 A AV saddr A addr16 3 8 A AV addr16 A HL ...

Page 205: ... saddr 2 4 saddr saddr 1 INCW rp 1 4 rp rp 1 DECW rp 1 4 rp rp 1 ROR A 1 1 2 CY A7 A0 Am 1 Am 1 ROL A 1 1 2 CY A0 A7 Am 1 Am 1 RORC A 1 1 2 CY A0 A7 CY Am 1 Am 1 ROLC A 1 1 2 CY A7 A0 CY Am 1 Am 1 SET1 saddr bit 3 6 saddr bit 1 sfr bit 3 6 sfr bit 1 A bit 2 4 A bit 1 PSW bit 3 6 PSW bit 1 HL bit 2 10 HL bit 1 CLR1 saddr bit 3 6 saddr bit 0 sfr bit 3 6 sfr bit 0 A bit 2 4 A bit 0 PSW bit 3 6 PSW bi...

Page 206: ...saddr16 2 6 PC PC 2 jdisp8 if Z 1 BNZ saddr16 2 6 PC PC 2 jdisp8 if Z 0 BT saddr bit addr16 4 10 PC PC 4 jdisp8 if saddr bit 1 sfr bit addr16 4 10 PC PC 4 jdisp8 if sfr bit 1 A bit addr16 3 8 PC PC 3 jdisp8 if A bit 1 PSW bit addr16 4 10 PC PC 4 jdisp8 if PSW bit 1 BF saddr bit addr16 4 10 PC PC 4 jdisp8 if saddr bit 0 sfr bit addr16 4 10 PC PC 4 jdisp8 if sfr bit 0 A bit addr16 3 8 PC PC 3 jdisp8...

Page 207: ...te addr16 1 None A ADD ADDC SUB SUBC AND OR XOR CMP MOVNote XCHNote ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV ADD ADDC SUB SUBC AND OR XOR CMP MOV MOV XCH MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP ROR ROL RORC ROLC r MOV MOV INC DEC B C DBNZ sfr MOV MOV saddr MOV ADD ADDC SUB SUBC AND OR XOR CMP MOV DBNZ INC DEC ad...

Page 208: ...ote saddrp SP None AX ADDW SUBW CMPW MOVW XCHW MOVW MOVW rp MOVW MOVWNote INCW DECW PUSH POP saddrp MOVW SP MOVW Note Only when rp BC DE or HL 3 Bit manipulation instructions SET1 CLR1 NOT1 BT BF 2nd Operand 1st Operand addr16 None A bit BT BF SET1 CLR1 sfr bit BT BF SET1 CLR1 saddr bit BT BF SET1 CLR1 PSW bit BT BF SET1 CLR1 HL bit SET1 CLR1 CY SET1 CLR1 NOT1 ...

Page 209: ...D 209 4 Call instructions branch instructions CALL CALLT BR BC BNC BZ BNZ DBNZ 2nd Operand 1st Operand AX addr16 addr5 addr16 Basic Instructions BR CALL BR CALLT BR BC BNC BZ BNZ Compound Instructions DBNZ 5 Other instructions RET RETI NOP EI DI HALT STOP ...

Page 210: ...isfied when the flash memory is written When supply voltage rises VPP must exceed VDD 10 µs or more after VDD has reached the lower limit value 4 0 V of the operating voltage range see a in the figure below When supply voltage drops VDD must be lowered 10 µs or more after VPP falls below the lower limit value 4 0 V of the operating voltage range of VDD see b in the figure below 4 0 V VDD 0 V 0 V V...

Page 211: ...ine through which a high fluctuating current flows Always make the ground point of the oscillator capacitor the same potential as VSS0 Do not ground the capacitor to a ground pattern through which a high current flows Do not fetch signals from the oscillator Remark For the resonator selection and oscillator constant customers are required to either evaluate the oscillation themselves or apply to t...

Page 212: ...h VOH2 USBDM USBDP TA 0 to 70 C RL 15 kΩ connected to VSS Note 2 8 V VOL1 Pins other than USBDM and USBDP IO 10 mA 1 0 V Output voltage low VOL2 USBDM USBDP TA 0 to 70 C RL 15 kΩ connected to VDD Note 0 3 V ILIH1 Pins other than X1 X2 USBDM and USBDP VI VDD 3 µA ILIH2 X1 X2 VI VDD 20 µA Input leakage current high ILIH3 USBDM USBDP TA 0 to 70 C 0 V VI VREG 10 µA ILIL1 Pins other than X1 X2 USBDM an...

Page 213: ... ROM Version IDD3 STOP mode When the USB function is enabled TA 0 to 70 C 50 100 µA IDD1 6 0 MHz crystal oscillation operating mode Note 2 5 0 10 0 mA IDD2 6 0 MHz crystal oscillation HALT mode Note 2 1 5 3 5 mA When the USB function is disabled 10 30 µA Supply currentNote 1 µPD78F9801 IDD3 STOP mode When the USB function is enabled TA 0 to 70 C 50 100 µA Notes 1 The power supply current does not ...

Page 214: ...pFNote 75 ns USBDM and USBDP rise time tR CL 350 pFNote 300 ns CL 50 pFNote 75 ns USBDM and USBDP fall time tF CL 350 pFNote 300 ns tR and tF matching tRFM tR tF 80 120 Differential output signal cross over point VCRS 1 3 2 0 V Data transfer rate tDRATE When the microcontroller operates at the system clock fX of 6 0 MHz 1 5 1 5 1 5 Mbps tUDJ1 Upon transferring the next bit 95 0 95 ns Transmission ...

Page 215: ...667 ns SI10 setup time tSIK1 To SCK10 150 ns When TPS100Note 1 0 333 ns SI10 hold time tKSI1 From SCK10 When TPS100Note 1 1 667 ns SO10 output delay tKSO1 From SCK10 CL 100 pFNote 2 0 200 ns Notes 1 Bit 4 of serial operation mode register 10 CSIM10 2 CL is the capacitance of the SO output line ii SCK10 External clock output Parameter Symbol Conditions MIN TYP MAX Unit SCK10 cycle time tKCY2 667 ns...

Page 216: ...216 AC Timing Measurement Points Except X1 Input and USB Function 0 8VDD 0 2VDD 0 8VDD 0 2VDD Measurement points Clock timing 1 fX tXL tXH X1 input VIH3 MIN VIL3 MAX TI Timing TI01 tTIL tTIH 1 fTI Interrupt Input Timing INTP0 tINTL tINTH RESET Input Timing RESET tRSL ...

Page 217: ...n differential signal jitter Next bit Bit following the next bit 667 ns 1 333 ns tUDJ1 tUDJ2 USBDM USBDP Differential output signal cross over point transmission EOP width reception EOP width and reception USB reset width tEOPT1 tEOPRm tURESm USBDM USBDP VCRS m 1 2 3 wire serial I O mode tKCYm tKLm tKHm SCK10 0 8VDD 0 2VDD tSIKm tKSIm tKSOm Input data Output data SI10 SO10 m 1 2 ...

Page 218: ...o prevent them from becoming unstable upon the start of oscillation 2 2 12 fX 2 15 fX or 2 17 fX can be selected according to the setting of bits 0 to 2 OSTS0 to OSTS2 of the oscillation stabilization time selection register Remark fX System clock oscillation frequency Data Hold timing STOP Mode Release by RESET VDD Data hold mode STOP mode HALT mode Internal reset operation Operating mode tSREL t...

Page 219: ...80 8ES 2 J I H N A 12 0 0 2 B 10 0 0 2 C 10 0 0 2 D 12 0 0 2 F G H 1 0 0 37 1 0 I J K 0 8 T P 1 0 0 2 0 20 L 0 5 M 0 17 S T U 1 6 MAX 0 25 T P 0 6 0 15 R 3 0 08 0 07 0 03 0 06 4 3 detail of lead end F G K M M P 1 4 0 05 NOTE S S A B C D U R S P Q L T Each lead centerline is located within 0 20 mm of its true position T P at maximum material condition ...

Page 220: ...s µ µ µ µPD789800GB 8ES 44 pin plastic LQFP 10 10 µ µ µ µPD78F9801GB 8ES 44 pin plastic LQFP 10 10 Soldering Method Soldering Conditions Symbol Infrared reflow Package peak temperature 235 C Time 30 seconds max at 210 C or higher Count Twice or less IR35 00 2 VPS Package peak temperature 215 C Time 40 seconds max at 200 C or higher Count Twice or less VP15 00 2 Wave soldering Solder bath temperatu...

Page 221: ... development tools Support of the PC98 NX series Unless otherwise stated the µPD789800 Subseries which is supported by IBM PC AT and compatibles can be used for the PC98 NX series When using the PC98 NX series refer to the descriptions of IBM PC AT and compatibles Windows Unless otherwise stated Windows indicates the following OSs Windows 3 1 Windows 95 98 2000 Windows NT TM Ver 4 0 ...

Page 222: ...r In circuit emulator Emulation board Emulation probe Conversion socket or conversion adapter Target system Flash programmer Flash memory writing adapter Flash memory Power supply unit Software package Control software Project Manager Windows version only Note 2 Software package Flash memory writing environment Notes 1 C library source file is not included in the software package 2 Project Manager...

Page 223: ... package Part number µS RA78K0S Program that converts a program written in C language into object codes that can be executed by a microcontroller Used in combination with an assembler package RA78K0S and device file DF789801 both sold separately Caution when used in PC environment The C compiler package is a DOS based application but may be used in the Windows environment by using the Project Mana...

Page 224: ... 4 Solaris Rel 2 5 1 1 4 inch CGMT A 3 Control Software Project Manager Control software created for efficient development of the user program in the Windows environment User program development operations such as editor startup build and debugger startup can be performed from the Project Manager Caution The Project Manager is included in the assembler package RA78K0S The Project Manager is used o...

Page 225: ...notebook PC as host machine PCMCIA socket supported IE 70000 PC IF C Interface adapter Interface adapter necessary when using IBM PC AT compatible as host machine ISA bus supported IE 70000 PCI IF A Interface adapter Adapter necessary when using personal computer incorporating PCI bus as host machine IE 789801 NS EM1 Emulation board Board for emulating the peripheral hardware inherent to the devic...

Page 226: ... while simulating the operation of the target system on the host machine Using SM78K0S the logic and performance of the application can be verified independently of hardware development Therefore the development efficiency can be enhanced and the software quality can be improved Used in combination with a device file DF789801 sold separately SM78K0S System simulator Part number µS SM78K0S File con...

Page 227: ...en designing a system Figure A 2 Distance Between In Circuit Emulator and Conversion Adapter Conversion adapter In circuit emulator IE 78K0S NS or IE 78K0S NS A Emulation board IE 789801 NS EM1 CN1 170 mmNote Emulation probe NP 44GB TQ NP H44GB TQ Target system TGB 044SAP Note Distance when NP 44GB TQ is used When NP H44GB TQ is used the distance is 370 mm Remarks 1 NP 44GB TQ and NP H44GB TQ are ...

Page 228: ...on of Target System NP H44GB TQ Emulation board IE 789801 NS EM1 Emulation probe NP H44GB TQ Conversion adapter TGB 044SAP 11 mm 34 mm 40 mm 10 mm 23 mm Target system Remarks 1 NP H44GB TQ is a product of Naito Densei Machida Mfg Co Ltd 2 TGB 044SAP is a product of TOKYO ELETECH CORPORATION ...

Page 229: ...nter DRXCON 106 Data handshake packet receive mode register URXMOD 109 Data packet transmit byte number counter DTXCO0 DTXCO1 106 Data handshake PID compare register DIDCMP 108 E External interrupt mode register 0 INTM0 168 H Handshake packet transmit reservation register HTXRSV 116 I Interrupt mask flag register 0 MK0 168 Interrupt mask flag register 1 MK1 168 Interrupt request flag register 0 IF...

Page 230: ...ister REMWUP 121 S Serial operation mode register 10 CSIM10 157 T Timer clock select register 2 TCL2 93 Token address compare register ADRCMP 107 Token packet receive result store register TRXRSL 113 Token PID compare register TIDCMP 106 Transmit receive shift register 10 SIO10 155 Transmit data bank 0 address USBT00 to USBT07 104 Transmit data bank 1 address USBT10 to USBT17 104 Transmit data PID...

Page 231: ...r 106 DTXRSV Data packet transmit reservation register 115 H HTXRSV Handshake packet transmit reservation register 116 I IF0 Interrupt request flag register 0 167 IF1 Interrupt request flag register 1 167 INTM0 External interrupt mode register 0 168 K KRM00 Key return mode register 00 170 M MK0 Interrupt mask flag register 0 168 MK1 Interrupt mask flag register 1 168 O OSTS Oscillation settling ti...

Page 232: ...t timer mode control register 01 83 TRXRSL Token packet receive result store register 113 U URXMOD Data handshake packet receive mode register 109 USBMOD USB receiver enable register 109 USBPOB USBPOW Transmit receive pointer 101 USBR0 to USBR7 Receive data address 103 USBRAL USBRAH Receive token address 102 USBRD Receive data PID 103 USBRTP Receive token PID 102 USBTCL USB timer start reservation...

Page 233: ...s register RXSTAT Modification of each bit of RXSTAT from reserved words to non reserved words in packet receive status register format Modification of note in Format of Packet Receive Status Register Modification of flag names in Conditions in Transmit Reservation CHAPTER 8 USB FUNCTION Modification of contents in block diagram of regulator and USB driver receiver CHAPTER 10 REGULATOR Addition of...

Page 234: ...eration Addition of Table 8 4 List of Sources of Interrupts from USB Function Correction of incorrect flag name in 8 6 Interrupt Request from USB Function Addition of description on USB reset Resume detection interrupt INTUSBRE Addition of 8 7 USB Function Control CHAPTER 8 USB FUNCTION Modification of Figure 10 1 Block Diagram of Regulator and USB Driver Receiver and Cautions CHAPTER 10 REGULATOR...

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