μ
PD720210
2. Pin Function
R19UH0093EJ0200 Rev.2.00
Page 6 of 59
May 26, 2014
2. Pin Function
This section describes each pin function.
Strapping information in the tables shows how the pin can be used to configure the functional settings of this
controller when the pin is pulled up/down, as detected at the end of chip reset. Refer to Chapter 5 for a
complete description of all available pin strap settings. Also refer to Section 3.4 for a list of chip configuration
settings available via external SPI ROM (optional).
2.1 Power
Supply
Pin Name
Pin No.
I/O
Type
Function
VDD10
5, 11, 14,
22, 28, 31,
47, 64, 67,
70
Power
1.05 V power supply for Core Logic
VDD33
8, 17, 25,
34, 42, 61,
76
Power
3.3 V power supply for IO buffer
AVDD33
71
Power
3.3 V power supply for Analog circuit
V50IN 49
Power
LDO Regulator 5 V Input
Need to be connected to GND, when integrated LDO is not
used.
V33OUT 48
Power
LDO 3.3 V Output
15 k
Ω
and 4.7
μ
F are required between this pin and GND,
when integrated LDO is not used.
AVDD33R
50
Power
SW Regulator 3.3 V Input
NGDRV
52
-
SW Regulator Nch FET Control (Note)
PGDRV
51
-
SW Regulator Pch FET Control (Note)
ILIM
53
-
SW Regulator Current Sense
V10FB
54
-
SW Regulator Output Monitor
Note:
See section 7.10 for important information about the selection of FET.
Summary of Contents for Renesas mPD720210
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