μ
PD720210
1. Overview
R19UH0093EJ0200 Rev.2.00
Page 4 of 59
May 26, 2014
Table 1-1. Terminology
Block Name
Description
SS PHY
SuperSpeed transceiver
HS/FS/LS PHY
High-/Full-/Low-speed transceiver
VBUS Monitor
Monitors the VBUS voltage level of the upstream port.
SS US Port
Control
Upstream port control logic for SuperSpeed
HS/FS/LS US
Port Control
Upstream port control logic for High-/Full-/Low-speed
SS Hub Core
Central control logic for SS-Hub.
HS/FS/LS Hub
Core
Central control logic for HS/FS/LS Hub.
SS DS Port
Control
Downstream port control logic for SuperSpeed
HS/FS/LS DS
Port Control
Downstream port control logic for HS/FS/LS
VBUS Control
Controls all the external port power switches
SPI Interface
Connected to external serial ROM which can hold the optional firmware and hub settings
SW-Regulator
Switching regulator control logic to output 1.05 V power from 5 V input, utilizing the
external transistor
LDO
Integrated Low Drop Out regulator to output 3.3 V power from 5 V input.
Summary of Contents for Renesas mPD720210
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