QB-V850ESFJ3 Preliminary User’s Manual ZUD-CD-05-0149 39/57
4.5 Cautions on DBPC, DBPSW, and ECR Registers
The DBPC, DBPSW, and ECR registers cannot be accessed during a break.
If a value is written to any of these registers during a break, the written value is ignored.
If these registers are read, 0 is always read.
4.6 Cautions on Trace Display Sequence
When the trace mode that displays the access history is used, the display sequence may be reversed.
•
If read and write instructions are successively executed
•
If a bit manipulation instruction that executes read-modify-write is executed (such as SET, NOT, or CLR)
In both the cases, the trace results of write and read are displayed in that order.
4.7 Cautions on Extension Probe
When using the external bus interface with the extension probe, add a data wait state by increasing the set value
of the DWC register by one.
4.8 Simultaneously Executing Two Instructions When Hardware Break Is Set
If a hardware break is set at the first or the next of two instructions that are executed at the same time, the
following phenomena may occur.
•
Break occurs at a place different from where it has been set.
•
The set break does not occur.
To prevent these phenomena, set a software break.
The conditions under which two instructions are simultaneously executed are shown on the following pages.
