NEC PG-FPL, User Manual

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Chapter 7 Notes on Target System
Preliminary User’s Manual U17271EE1V0UM00
The following shows an example of the interface circuit of UART (asynchronous communication port).
Refer to the above design proposal for the pin processing of the device to be used.
Figure 7-1: Example of UART Interface Circuit
Cautions: 1. The FPL operates normally if a direct connection between PG-FPL and the device
is established. No additional external components like pull up or pull down resis-
tors need to be connected to the signals between PG-FPL and the device.
2. Special care have to be taken if pull up or pull down resistors are attached to any
signal between PG-FPL and the device.
PG-FPL drive some signals by internal pull up or pull down resistors to
high or low level. Especially the FLMD0 (4.7 K pull up), FLMD1 (100 pull down),
TXD (~5 K pull up), RESET (~5K pull up) signals may be corrupted by an external
circuitry.
Please check the compatibility of external components to the internal circuitry
shown on page 90 of Chapter 8
Circuit Diagrams.
GND
RESET
RXD
VDD
TXD
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
VDD2
FLMD1
FLMD0
RESET
RXD
TXD
FLMD1
FLMD0
VDD
VSS
X1
X2
C
C
Y
VCC
VCC VCC VCC
Jumper
R R
R
R R
IC
Microcontroller
User reset circuit