µ
PD75P3116
37
Data Sheet U11369EJ3V0DS
AC Characteristics (T
A
= –40 to +85˚C, V
DD
= 1.8 to 5.5 V)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
CPU clock cycle
t
CY
Operating on
V
DD
= 2.7 to 5.5 V
0.67
64
µ
s
time
Note 1
main system clock
V
DD
= 1.8 to 5.5 V
0.95
64
µ
s
(Min. instruction execution
Operating on subsystem clock
114
122
125
µ
s
time = 1 machine cycle)
TI0, TI1, TI2 input
f
TI
V
DD
= 2.7 to 5.5 V
0
1.0
MHz
frequency
V
DD
= 1.8 to 5.5 V
0
275
kHz
TI0, TI1, TI2 input
t
TIH
, t
TIL
V
DD
= 2.7 to 5.5 V
0.48
µ
s
high-/low-level width
V
DD
= 1.8 to 5.5 V
1.8
µ
s
Interrupt input high-/
t
INTH
, t
INTL
INT0
IM02 = 0
Note 2
µ
s
low-level width
IM02 = 1
10
µ
s
INT1, 2, 4
10
µ
s
KR0 to KR7
10
µ
s
RESET low-level width
t
RSL
10
µ
s
Notes 1.
The cycle time (minimum instruction
execution time) of the CPU clock
(
Φ
) is determined by the oscillation
frequency of the connected
resonator (and external clock), the
system clock control register (SCC)
and the processor clock control
register (PCC). The figure on the
right indicates the cycle time t
CY
versus supply voltage V
DD
characteristics with the main system
clock operating.
2.
2t
CY
or 128/fx is set by setting the
interrupt mode register (IM0).
1
0
2
3
4
5
6
0.5
1
3
2
4
5
6
60
64
Supply voltage V
DD
[V]
t
CY
vs. V
DD
(Main system clock operation)
Cycle time t
CY
[
µ
s]
Guaranteed operation
range
