NEC PD75P3116 Datasheet Download

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PD75P3116

Data Sheet U11369EJ3V0DS

4. Mk I AND Mk II MODE SELECTION FUNCTION

Setting the stack bank selection (SBS) register for the

PD75P3116 enables the program memory to be switched

between the Mk I mode and Mk II mode. This function is applicable when using the

PD75P3116 to evaluate the

PD753104, 753106, or 753108.

When bit 3 of SBS is set to 1: Sets the Mk I mode (supports the Mk I mode for the

PD753104, 753106, and 753108)

When bit 3 of SBS is set to 0: Sets the Mk II mode (supports the Mk II mode for the

PD753104, 753106, and 753108)

4.1 Differences Between Mk I Mode and Mk II Mode

Table 4-1 lists the differences between the Mk I mode and the Mk II mode for the

PD75P3116.

Table 4-1. Differences Between Mk I Mode and Mk II Mode

Item

Mk I Mode

Mk II Mode

Program counter

13-0

Program memory (bytes)

16384

Data memory (bits)

512

Stack

Stack bank

Selectable via memory banks 0 and 1

No. of stack bytes

2 bytes

3 bytes

Instruction

BRA !addr1 instruction

Not available

Available

CALLA !addr1 instruction

Instruction

CALL !addr instruction

3 machine cycles

4 machine cycles

execution time CALLF !faddr instruction

2 machine cycles

3 machine cycles

Supported mask ROM products

When set to Mk I mode:

When set to Mk II mode:

PD753104, 753106, and 753108

Caution

The Mk II mode supports a program area exceeding 16 KB for the 75X and 75XL Series. Therefore, this

mode is effective for enhancing software compatibility with products that have a program area of more

than 16 KB.

With regard to the number of stack bytes during execution of subroutine call instructions, the usable

area increases by 1 byte per stack compared to the Mk I mode when the Mk II mode is selected.

However, when the CALL !addr and CALLF !faddr instructions are used, the machine cycle becomes

longer by 1 machine cycle. Therefore, if more emphasis is placed on RAM use efficiency and

processing performance than on software compatibility, the Mk I mode should be used.

Summary of Contents for PD75P3116

Page 1: ...ocontrollers are microcontrollers with on chip one time PROM that are totally supported by NEC This support includes writing application programs marking screening and verification ORDERING INFORMATION Part Number Package µPD75P3116GC AB8 64 pin plastic QFP 14 14 µPD75P3116GK 8A8 64 pin plastic LQFP 12 12 µPD75P3116GC 8BS 64 pin plastic LQFP 14 14 Caution This device does not provide an internal p...

Page 2: ... 2 duty 1 2 bias 1 3 duty 1 2 bias 1 3 duty 1 3 bias 1 4 duty 1 3 bias Timers 5 channels 8 bit timer event counter 3 channels Can be used as 16 bit timer event counter carrier generator and timer with gate Basic interval timer watchdog timer 1 channel Watch timer 1 channel Serial interface 3 wire serial I O mode MSB LSB first switchable 2 wire serial I O mode SBI mode Bit sequential buffer BSB 16 ...

Page 3: ...ENCES BETWEEN µPD75P3116 AND µPD753104 753106 753108 16 6 MEMORY CONFIGURATION 17 7 INSTRUCTION SET 19 8 ONE TIME PROM PROGRAM MEMORY WRITE AND VERIFY 28 8 1 Operation Modes for Program Memory Write Verify 28 8 2 Program Memory Write Procedure 29 8 3 Program Memory Read Procedure 30 8 4 One Time PROM Screening 31 9 ELECTRICAL SPECIFICATIONS 32 10 CHARACTERISTIC CURVES REFERENCE VALUES 47 11 PACKAG...

Page 4: ...0 P83 S20 39 P82 S21 38 P81 S22 37 P80 S23 36 P23 BUZ 35 P22 PCL PTO2 34 P21 PTO1 33 P20 PTO0 64 COM3 63 COM2 62 COM1 61 COM0 60 S0 59 S1 58 S2 57 S3 56 S4 55 S5 54 S6 53 S7 52 S8 51 S9 50 S10 49 S11 1 BIAS 2 VLC0 3 VLC1 4 VLC2 5 P30 LCDCL MD0 6 P31 SYNC MD1 7 P32 MD2 8 P33 MD3 9 Vss 10 P50 D4 11 P51 D5 12 P52 D6 13 P53 D7 14 P60 KR0 D0 15 P61 KR1 D1 16 P62 KR2 D2 17 P63 KR3 D3 18 RESET 19 XT1 20 ...

Page 5: ...80 to P83 Port 8 PTO0 to PTO2 Programmable timer output 0 to 2 P90 to P93 Port 9 BUZ Buzzer clock KR0 to KR3 Key return 0 to 3 PCL Programmable clock SCK Serial clock INT0 1 4 External vectored interrupt 0 1 4 SI Serial input INT2 External test input 2 SO Serial output X1 X2 Main system clock oscillation 1 2 SB0 SB1 Serial data bus 0 1 XT1 XT2 Subsystem clock oscillation 1 2 RESET Reset VPP Progra...

Page 6: ...o P53 D7 P60 D0 to P63 D3 P80 to P83 Port 0 Port 1 Port 2 Port 3 Port 5 Port 6 Port 8 Port 9 P90 to P93 LCD controller driver 4 S16 P93 to S19 P90 4 S20 P83 to S23 P80 VLC0 VLC1 VLC2 SYNC P31 LCDCL P30 Clocked serial interface SI SB1 P03 INTCSI Interrupt control INT0 P10 SO SB0 P02 SCK P01 TOUT0 INT1 P11 INT4 P00 INT2 P12 TI1 TI2 P60 KR0 to P63 KR3 Bit sequential buffer 16 4 INT1 8 bit timer event...

Page 7: ...0 P20 I O PTO0 4 bit I O port Port 2 Input E B Connection of an internal pull up resistor can be P21 PTO1 specified by a software setting in 4 bit units P22 PCL PTO2 P23 BUZ P30 I O LCDCL MD0 Programmable 4 bit I O port Port 3 Input E B Input and output can be specified in 1 bit units P31 SYNC MD1 Connection of an internal pull up resistor can be specified by a software setting in 4 bit units P32 ...

Page 8: ...s P62 KR2 D2 P63 KR3 D3 P80 I O S23 4 bit I O port Port 8 Input H Connection of an internal pull up resistor can be P81 S22 specified by a software setting in 4 bit unitsNote 2 P82 S21 P83 S20 P90 I O S19 Programmable 4 bit I O port Port 9 Input H Connection of an internal pull up resistor can be P91 S18 specified by a software setting in 4 bit unitsNote 2 P92 S17 P93 S16 Notes 1 Circuit types enc...

Page 9: ...ble input Asynchronous KR0 to KR3 I O P60 to P63 Parallel falling edge detection testable input Input F A X1 Input Ceramic crystal resonator connection for main system clock oscillation If using an external clock input the signal X2 to X1 and input the inverted signal to X2 XT1 Input Crystal resonator connection for subsystem clock oscillation If using an external clock input the signal to XT1 and...

Page 10: ...riving LCD BIAS Output Output for external split resistor cut Note 2 LCDCLNote 3 Output P30 MD0 Clock output for driving external expansion driver Input E B SYNCNote 3 Output P31 MD1 Clock output for synchronization of external expansion driver Input E B Notes 1 VLCX X 0 1 2 is selected as the input source for the display outputs as shown below S0 to S23 VLC1 COM0 to COM2 VLC2 COM3 VLC0 2 When the...

Page 11: ... P U R Type D Output disable P U R Pull Up Resistor Type A VDD P ch P U R enable P U R P U R Pull Up Resistor IN VDD P ch IN OUT P U R enable Data P U R Type D Output disable P U R Pull Up Resistor Type B CMOS standard input buffer Push pull output that can be set to high impedance output with both P ch and N ch OFF Schmitt triggered input with hysteresis characteristics Continued Type A Type D Ty...

Page 12: ... Data P U R Output disable P U R Pull Up Resistor N ch Pull up resistor that operates only when an input instruction is executed The current flows from VDD to a pin when the pin is at low level Note OUT N ch P ch N ch P ch N ch P ch N ch P ch N ch P ch N ch N ch VLC0 VLC1 SEG data VLC2 N ch P ch P ch N ch N ch N ch P ch P ch N ch OUT VLC0 VLC1 VLC2 COM data Voltage controller Output disable Data N...

Page 13: ...en P22 PTO2 PCL P23 BUZ P30 LCDCL MD0 P31 SYNC MD1 P32 MD2 P33 MD3 P50 D4 to P53 D7 Input Connect to Vss Output Connect to Vss P60 KR0 D0 to P63 KR3 D3 Input Independently connect to Vss or VDD via a resistor Output Leave open S0 to S15 Leave open COM0 to COM3 S16 P93 to S19 P90 Input Independently connect to Vss or VDD via a resistor S20 P83 to S23 P80 Output Leave open VLC0 to VLC2 Connect to Vs...

Page 14: ...banks 0 and 1 No of stack bytes 2 bytes 3 bytes Instruction BRA addr1 instruction Not available Available CALLA addr1 instruction Instruction CALL addr instruction 3 machine cycles 4 machine cycles execution time CALLF faddr instruction 2 machine cycles 3 machine cycles Supported mask ROM products When set to Mk I mode When set to Mk II mode µPD753104 753106 and 753108 µPD753104 753106 and 753108 ...

Page 15: ... BNote at the beginning of the program When using the Mk II mode be sure to initialize it to 000 BNote Note Set the desired value for Figure 4 1 Format of Stack Bank Selection Register Caution SBS3 is set to 1 after RESET input and consequently the CPU operates in the Mk I mode When using instructions for the Mk II mode set SBS3 to 0 and set the Mk II mode before using the instructions SBS3 SBS2 S...

Page 16: ...44 8192 16384 Data memory 4 bits 512 Mask options Pull up resistor for Available Not available Port 5 On chip not on chip can be specified Not on chip Split resistor for LCD driving power supply Wait time after Available Not available RESET Selectable between 217 fX and 215 fX Note Fixed to 215 fX Note Feedback resistor Available Not available of subsystem clock Use not use can be selected Enable ...

Page 17: ...er 6 bits INT1 start address lower 8 bits INTCSI start address higher 6 bits INTCSI start address lower 8 bits INTT0 start address higher 6 bits INTT0 start address lower 8 bits INTT1 INTT2 start address higher 6 bits INTT1 INTT2 start address lower 8 bits Reference table for GETI instruction 0000H 0002H 0004H 0006H 0008H 000AH 000CH 0020H 007FH 0080H 07FFH 0800H 0FFFH 1000H 1FFFH 2000H 2FFFH 3000...

Page 18: ...e selected as the stack area 32 4 256 4 224 4 128 4 0 1 15 000H 01FH 020H 0FFH 100H 1E0H 1DFH 1F7H 1F8H F80H FFFH General purpose register area Display data memory Data area static RAM 512 4 Stack areaNote Peripheral hardware area Data memory Memory bank Not incorporated 1FFH 256 4 224 4 24 4 8 4 ...

Page 19: ...t can be entered for fmem and pmem are restricted Representation Coding Format reg X A B C D E H L reg1 X B C D E H L rp XA BC DE HL rp1 BC DE HL rp2 BC DE rp XA BC DE HL XA BC DE HL rp 1 BC DE HL XA BC DE HL rpa HL HL HL DE DL rpa1 DE DL n4 4 bit immediate data or label n8 8 bit immediate data or label mem 8 bit immediate data or labelNote bit 2 bit immediate data or label fmem FB0H to FBFH FF0H ...

Page 20: ...gister pair BC DE Expansion register pair DE HL Expansion register pair HL PC Program counter SP Stack pointer CY Carry flag bit accumulator PSW Program status word MBE Memory bank enable flag RBE Register bank enable flag PORTn Port n n 0 to 3 5 6 8 9 IME Interrupt master enable flag IPS Interrupt priority selection register IE Interrupt enable flag RBS Register bank selection register MBS Memory...

Page 21: ...te 3 byte instructions BR addr BRA addr1 CALL addr and CALLA addr1 Caution The GETI instruction is skipped for one machine cycle One machine cycle equals one cycle tCY of the CPU clock Φ Use the PCC setting to select from among four cycle times MB 0 000H to 07FH MB 15 F80H to FFFH MB MBS MBS 0 1 15 MB MBE MBS MBS 0 1 15 1 MB 0 2 MBE 1 MBE 0 3 MB 15 fmem FB0H to FBFH FF0H to FFFH MB 15 pmem FC0H to...

Page 22: ... XA HL 2 2 XA HL 1 HL A 1 1 HL A 1 HL XA 2 2 HL XA 1 A mem 2 2 A mem 3 XA mem 2 2 XA mem 3 mem A 2 2 mem A 3 mem XA 2 2 mem XA 3 A reg 2 2 A reg XA rp 2 2 XA rp reg1 A 2 2 reg1 A rp 1 XA 2 2 rp 1 XA XCH A HL 1 1 A HL 1 A HL 1 2 S A HL then L L 1 1 L 0 A HL 1 2 S A HL then L L 1 1 L FH A rpa1 1 1 A rpa1 2 XA HL 2 2 XA HL 1 A mem 2 2 A mem 3 XA mem 2 2 XA mem 3 A reg1 1 1 A reg1 XA rp 2 2 XA rp Tabl...

Page 23: ... XA rp 2 2 XA CY XA rp CY rp 1 XA 2 2 rp 1 CY rp 1 XA CY SUBS A HL 1 1 S A A HL 1 borrow XA rp 2 2 S XA XA rp borrow rp 1 XA 2 2 S rp 1 rp 1 XA borrow SUBC A HL 1 1 A CY A HL CY 1 XA rp 2 2 XA CY XA rp CY rp 1 XA 2 2 rp 1 CY rp 1 XA CY AND A n4 2 2 A A n4 A HL 1 1 A A HL 1 XA rp 2 2 XA XA rp rp 1 XA 2 2 rp 1 rp 1 XA OR A n4 2 2 A A v n4 A HL 1 1 A A v HL 1 XA rp 2 2 XA XA v rp rp 1 XA 2 2 rp 1 rp ...

Page 24: ...kip if mem bit 1 3 mem bit 1 fmem bit 2 2 S Skip if fmem bit 1 4 fmem bit 1 pmem L 2 2 S Skip if pmem7 2 L3 2 bit L1 0 1 5 pmem L 1 H mem bit 2 2 S Skip if H mem3 0 bit 1 1 H mem bit 1 SKF mem bit 2 2 S Skip if mem bit 0 3 mem bit 0 fmem bit 2 2 S Skip if fmem bit 0 4 fmem bit 0 pmem L 2 2 S Skip if pmem7 2 L3 2 bit L1 0 0 5 pmem L 0 H mem bit 2 2 S Skip if H mem3 0 bit 0 1 H mem bit 0 SKTCLR fmem...

Page 25: ...ct the most appropriate instruction among the following BRA addr1 BR addr BRCB caddr BR addr1 addr 3 3 PC13 0 addr 6 addr 1 2 PC13 0 addr 7 addr1 1 2 PC13 0 addr1 PCDE 2 3 PC13 0 PC13 8 DE PCXA 2 3 PC13 0 PC13 8 XA BCDE 2 3 PC13 0 BCDENote 2 6 BCXA 2 3 PC13 0 BCXANote 2 6 BRANote 1 addr1 3 3 PC13 0 addr1 11 BRCB caddr 2 2 PC13 0 PC13 12 caddr11 0 8 Notes 1 The sections in double boxes are only sup...

Page 26: ...3 12 PC13 0 000 faddr SP SP 4 3 SP 6 SP 3 SP 4 PC11 0 SP 5 0 0 PC13 12 SP 2 X X MBE RBE PC13 0 000 faddr SP SP 6 RETNote 1 3 MBE RBE PC13 12 SP 1 PC11 0 SP SP 3 SP 2 SP SP 4 X X MBE RBE SP 4 PC11 0 SP SP 3 SP 2 0 0 PC13 12 SP 1 SP SP 6 RETSNote 1 3 S MBE RBE PC13 12 SP 1 Unconditional PC11 0 SP SP 3 SP 2 SP SP 4 then skip unconditionally X X MBE RBE SP 4 PC11 0 SP SP 3 SP 2 0 0 PC13 12 SP 1 SP SP ...

Page 27: ...1 3 When using TBR instruction 10 PC13 0 taddr 5 0 taddr 1 When using TCALL instruction SP 4 SP 1 SP 2 PC11 0 SP 3 MBE RBE PC13 12 PC13 0 taddr 5 0 taddr 1 SP SP 4 When using instruction other than Determined by TBR or TCALL referenced Execute taddr taddr 1 instructions instruction 1 3 When using TBR instruction 10 PC13 0 taddr 5 0 taddr 1 4 When using TCALL instruction SP 6 SP 3 SP 4 PC11 0 SP 5 ...

Page 28: ...3 Operation mode selection pin for program memory write verify D0 P60 to D3 P63 8 bit data I O pins for program memory write verify lower 4 bits D4 P50 to D7 P53 higher 4 bits VDD Pin where power supply voltage is applied Apply 1 8 to 5 5 V in normal operation mode and 6 V for program memory write verify Caution Pins not used for program memory write verify should be connected to Vss 8 1 Operation...

Page 29: ... mode If the data is written go to 8 and if not repeat 6 and 7 8 Additional write X Number of write operations from 6 and 7 1 ms 9 Apply four pulses to the X1 pin to increment the program memory address by one 10 Repeat 6 to 9 until the end address is reached 11 Select the program memory address zero clear mode 12 Return the VDD and VPP pin voltages to 5 V 13 Turn off the power The following figur...

Page 30: ...wn unused pins to VSS via resistors Set the X1 pin to low 2 Supply 5 V to the VDD and VPP pins 3 Wait 10 µs 4 Select the program memory address zero clear mode 5 Supply 6 V to VDD and 12 5 V to VPP 6 Select the verify mode Apply four pulses to the X1 pin The data stored in one address will be output every four clock pulses 7 Select the program memory address zero clear mode 8 Return the VDD and VP...

Page 31: ...er the required data is written and the PROM is stored under the temperature and time conditions shown below the PROM should be verified via screening Storage Temperature Storage Time 125 C 24 hours NEC offers QTOP microcontrollers for which one time PROM writing marking screening and verification are provided at additional cost For further details contact an NEC sales representative ...

Page 32: ...ating ambient TA 40 to 85Note C temperature Storage temperature Tstg 65 to 150 C Note When LCD is driven in normal mode TA 10 to 85 C Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter That is the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage and therefore the product must be...

Page 33: ... 1 8 V VDD 2 7 V and the oscillation frequency is 4 19 MHz fx 6 0 MHz setting the processor clock control register PCC to 0011 makes 1 machine cycle less than the required 0 95 µs Therefore set PCC to a value other than 0011 3 The oscillation stabilization time is necessary for oscillation to stabilize after applying VDD or releasing the STOP mode Caution When using the main system clock oscillato...

Page 34: ...the subsystem clock oscillator wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance Keep the wiring length as short as possible Do not cross the wiring with the other signal lines Do not route the wiring near a signal line through which a high fluctuating current flows Always make the ground point of the oscillator capacit...

Page 35: ...2 3 6 8 and 9 IOH 1 0 mA VDD 0 5 V Output voltage low VOL1 SCK SO Ports 2 3 5 6 8 and 9 IOL 15 mA 0 2 2 0 V VDD 4 5 to 5 5 V IOL 1 6 mA 0 4 V VOL2 SB0 SB1 When N ch open drain 0 2VDD V pull up resistor 1 kΩ Input leakage ILIH1 VIN VDD Pins other than X1 XT1 3 µA current high ILIH2 X1 XT1 20 µA ILIH3 VIN 13 V Port 5 N ch open drain 20 µA Input leakage ILIL1 VIN 0 V Pins other than X1 XT1 and Port 5...

Page 36: ...ode VDD 3 0 V 10 5 5 18 µA VDD 2 0 V 10 2 2 7 µA VDD 3 0 V TA 25 C 5 5 12 µA VDD 3 0 V 10 4 0 12 µA VDD 3 0 V 4 0 8 µA TA 25 C IDD5 XT1 0 VNote 10 VDD 5 0 V 10 0 05 10 µA STOP mode VDD 3 0 V TA 40 to 85 C 0 02 5 µA 10 TA 25 C 0 02 3 µA Notes 1 Set to VAC0 0 when the low current consumption mode and the stop mode are used If VAC0 1 is set the current increases for approx 1 µA 2 The voltage deviatio...

Page 37: ...µs Interrupt input high tINTH tINTL INT0 IM02 0 Note 2 µs low level width IM02 1 10 µs INT1 2 4 10 µs KR0 to KR7 10 µs RESET low level width tRSL 10 µs Notes 1 Thecycletime minimuminstruction execution time of the CPU clock Φ is determined by the oscillation frequency of the connected resonator and external clock the systemclockcontrolregister SCC and the processor clock control register PCC The f...

Page 38: ...l I O mode read this parameter as SB0 or SB1 instead 2 RL and CL are the load resistance and load capacitance of the SO output lines respectively 2 wire and 3 wire serial I O mode SCK External clock input TA 40 to 85 C VDD 1 8 to 5 5 V Parameter Symbol Test Conditions MIN TYP MAX Unit SCK cycle time tKCY2 VDD 2 7 to 5 5 V 800 ns VDD 1 8 to 5 5 V 3200 ns SCK high low level tKL2 tKH2 VDD 2 7 to 5 5 ...

Page 39: ...h level width tSBH tKCY3 ns Note RL and CL are the load resistance and load capacitance of the SB0 and SB1 output lines respectively SBI mode SCK External clock input slave TA 40 to 85 C VDD 1 8 to 5 5 V Parameter Symbol Test Conditions MIN TYP MAX Unit SCK cycle time tKCY4 VDD 2 7 to 5 5 V 800 ns VDD 1 8 to 5 5 V 3200 ns SCK high low level tKL4 tKH4 VDD 2 7 to 5 5 V 400 ns width VDD 1 8 to 5 5 V ...

Page 40: ...iming Test Points Excluding X1 XT1 Input Clock Timing TI0 TI1 TI2 Timing TI0 TI1 TI2 1 fTI tTIL tTIH X1 input 1 fX tXL tXH 0 1 V VDD 0 1 V XT1 input 1 fXT tXTL tXTH 0 1 V VDD 0 1 V VIH MIN VIL MAX VIH MIN VIL MAX VOH MIN VOL MAX VOH MIN VOL MAX ...

Page 41: ...heet U11369EJ3V0DS Serial Transfer Timing 3 wire serial I O mode 2 wire serial I O mode tKCY1 2 tKL1 2 tKH1 2 SCK SI SO tSIK1 2 tKSI1 2 tKSO1 2 Input data Output data tKSO1 2 tSIK1 2 tKL1 2 tKH1 2 SCK tKSI1 2 SB0 1 tKCY1 2 ...

Page 42: ... tKSO3 4 SCK SB0 1 tKL3 4 tSBK tKSB tKCY3 4 tKH3 4 tKSI3 4 tSIK3 4 tKSO3 4 SCK SB0 1 tKL3 4 tSBK tSBH tSBL tKSB Serial Transfer Timing Bus release signal transfer Command signal transfer Interrupt input timing RESET input timing tRSL RESET tINTL tINTH INT0 1 2 4 KR0 to 7 ...

Page 43: ...uest Note 2 ms Notes 1 The oscillation stabilization wait time is the time during which the CPU operation is stopped to prevent unstable operation at the start of oscillation 2 Depends on the basic interval timer mode register BTM settings see the table below BTM3 BTM2 BTM1 BTM0 Wait Time fx 4 19 MHz fx 6 0 MHz 0 0 0 220 fx approx 250 ms 220 fx approx 175 ms 0 1 1 217 fx approx 31 3 ms 217 fx appr...

Page 44: ...Release Signal STOP Mode Release by Interrupt Signal VDD RESET STOP instruction execution STOP mode Data retention mode Internal reset operation HALT mode Operating mode tSREL tWAIT tSREL tWAIT VDD STOP instruction execution STOP mode Data retention mode HALT mode Operating mode Standby release signal Interrupt request ...

Page 45: ...rom MD0 tAH 2 µs Data hold time from MD0 tDH 2 µs Data output float delay time from MD0 tDF 0 130 ns VPP setup time to MD3 tVPS 2 µs VDD setup time to MD3 tVDS 2 µs Initial program pulse width tPW 0 95 1 0 1 05 ms Additional program pulse width tOPW 0 95 21 0 ms MD0 setup time to MD1 tM0S 2 µs Data output delay time from MD0 tDV MD0 MD1 VIL 1 µs MD1 hold time from MD0 tM1H tM1H tM1R 50 µs 2 µs MD1...

Page 46: ...M1R tM0S tOPW tM1S tM1H tPCR tM3S tM3H Data input Data output Data input Data input VPP VDD VDD 1 VDD VPP VDD X1 D0 P60 to D3 P60 D4 P50 to D7 P53 MD0 P30 MD1 P31 MD2 P32 MD3 P33 tVPS tVDS VPP VDD VDD 1 VDD VPP VDD tXH tXL tHAD tDAD tDV tI tM3HR tDFR tPCR tM3SR X1 D0 P60 to D3 P60 D4 P50 to D7 P53 MD0 P30 MD1 P31 MD2 P32 MD3 P33 Data output Data output ...

Page 47: ...stem clock HALT mode 32 kHz oscillation XT1 XT2 X1 X2 Crystal resonator 6 0 MHz Crystalresonator 32 768 kHz 330 kΩ 22 pF 22 pF 22 pF 22 pF VDD VDD Main system clock STOP mode 32 kHz oscillation SOS 1 1 and subsystem clock HALT mode SOS 1 1 IDD vs VDD Main System Clock 6 0 MHz Crystal Resonator PCC 0011 Main system clock STOP mode 32 kHz oscillation SOS 1 0 and subsystem clock HALT mode SOS 1 0 Sub...

Page 48: ...oltage VDD V Supply current I DD mA VDD VDD PCC 0010 Main system clock HALT mode 32 kHz oscillation Subsystem clock HALT mode SOS 1 0 and main system clock STOP mode 32 kHz oscillation SOS 1 0 Subsystem clock operation mode SOS 1 0 IDD vs VDD Main System Clock 4 19 MHz Crystal Resonator TA 25 C Main system clock STOP mode 32 kHz oscillation SOS 1 1 and subsystem clock HALT mode SOS 1 1 PCC 0001 PC...

Page 49: ...m of its true position T P at maximum material condition ITEM MILLIMETERS A B D G 17 6 0 4 14 0 0 2 0 8 T P 1 0 J 17 6 0 4 K P64GC 80 AB8 5 C 14 0 0 2 I 0 15 1 8 0 2 L 0 8 0 2 F 1 0 N P Q 0 10 2 55 0 1 0 1 0 1 R S 5 5 2 85 MAX H 0 37 0 08 0 07 M 0 17 0 08 0 07 S S N J detail of lead end C D A B R K M L P I S Q G F M H 11 PACKAGE DRAWINGS ...

Page 50: ...position T P at maximum material condition ITEM MILLIMETERS A B D G 14 8 0 4 12 0 0 2 0 13 1 125 I 14 8 0 4 J C 12 0 0 2 H 0 32 0 08 0 65 T P K 1 4 0 2 L 0 6 0 2 F 1 125 P64GK 65 8A8 3 N P Q 0 10 1 4 0 1 0 125 0 075 R S 5 5 1 7 MAX M 0 17 0 08 0 07 48 49 32 64 1 17 16 33 S S N J detail of lead end C D A B R K M L P I S Q G F M H ...

Page 51: ... P at maximum material condition ITEM MILLIMETERS A B D G 17 2 0 2 14 0 0 2 0 8 T P 1 0 J 17 2 0 2 K C 14 0 0 2 I 0 20 1 6 0 2 L 0 8 F 1 0 N P Q 0 10 1 4 0 1 0 127 0 075 U 0 886 0 15 R S 3 1 7 MAX T 0 25 P64GC 80 8BS H 0 37 0 08 0 07 M 0 17 0 03 0 06 S N J T detail of lead end C D A B K M I S P R L U Q G F M H 4 3 1 64 49 17 32 16 48 33 S ...

Page 52: ... max package surface temperature Partial heating Pin temperature 300 C max Time 3 seconds max per pin row Caution Do not use different soldering methods together except for partial heating 2 µPD75P3116GK 8A8 64 pin plastic LQFP 12 12 Soldering Soldering Conditions Recommended Method Condition Symbol Infrared reflow Package peak temperature 235 C Time 30 seconds max at 210 C or higher IR35 107 2 Co...

Page 53: ...onds max at 210 C or higher IR35 00 2 Count Twice or less VPS Package peak temperature 215 C Time 40 seconds max at 200 C or higher VP15 00 2 Count Twice or less Wave soldering Solder bath temperature 260 C max Time 10 seconds max Count Once WS60 00 1 Preheating temperature 120 C max package surface temperature Partial heating Pin temperature 300 C max Time 3 seconds max per pin row Caution Do not...

Page 54: ...ailable When Mk I mode Unavailable CALLA addr1 When Mk II mode Available MOVT XA BCDE Available MOVT XA BCXA BR BCDE BR BCXA CALL addr 3 machine cycles Mk I mode 3 machine cycles Mk II mode 4 machine cycles CALLF faddr 2 machine cycles Mk I mode 2 machine cycles Mk II mode 3 machine cycles I O ports CMOS input 8 8 CMOS I O 16 20 Bit port output 8 0 N ch open drain I O 8 4 Total 40 32 LCD controlle...

Page 55: ... are available 3 wire serial I O mode MSB LSB can be selected for transfer first bit 2 wire serial I O mode SBI mode SOS register Feedback resistor None Contained cut flag SOS 0 Sub oscillator current None Contained cut flag SOS 1 Register bank selection register RBS None Yes Standby release by INT0 No Yes Vectored interrupts External 3 Internal 3 External 3 Internal 5 Supply voltage VDD 2 0 to 6 ...

Page 56: ...800 Series MS DOSTM 3 5 2HD µS5A13RA75X Ver 3 30 to Ver 6 2Note IBM PC AT Refer to OS for 3 5 2HC µS7B13RA75X or compatibles IBM PCs Device file Host Machine Part Number OS Supply Medium Product Name PC 9800 Series MS DOS 3 5 2HD µS5A13DF753108 Ver 3 30 to Ver 6 2Note IBM PC AT Refer to OS for 3 5 2HC µS7B13DF753108 or compatibles IBM PCs Note Ver 5 00 and later include a task swapping function bu...

Page 57: ...µPD75P3116GK 8A8 It can be used when connected to the PG 1500 PA 75P3116GC 8BS This is a PROM programmer adapter for the µPD75P3116GC 8BS It can be used when connected to the PG 1500 Software PG 1500 controller Connects the PG 1500 to the host machine via serial and parallel interfaces and controls the PG 1500 on the host machine Host machine Part number OS Supply medium Product name PC 9800 Serie...

Page 58: ...n conversion socket EV 9200GC 64 to facilitate connection with the target system EP 753108GK R This is an emulation probe for the µPD75P3116GK When being used it is connected with the IE 75001 R and the IE 75300 R EM TGK 064SBW It includes a 64 pin conversion adapter TGK 064SBW to facilitate connection with the target system Software IE control program This program can control the IE 75001 R on a ...

Page 59: ...BM PCs are supported OS Version PC DOSTM Ver 3 1 to 6 3 J6 1 VNote to J6 3 VNote MS DOS Ver 5 0 to 6 2 5 0 VNote to 6 2 VNote IBM DOSTM J5 02 VNote Note Only English mode is supported Caution Ver 5 0 and later include a task swapping function but this function cannot be used in this software ...

Page 60: ... EV 9200GC 64 B D C M N L K R Q I H P O S T J G No 1 pin index EV 9200GC 64 G0E ITEM MILLIMETERS INCHES A B C D E F G H I J K L M N O P Q R S T 18 8 14 1 14 1 18 8 4 C 3 0 0 8 6 0 15 8 18 5 6 0 15 8 18 5 8 0 7 8 2 5 2 0 1 35 0 35 0 1 2 3 1 5 0 74 0 555 0 555 0 74 4 C 0 118 0 031 0 236 0 622 0 728 0 236 0 622 0 728 0 315 0 307 0 098 0 079 0 053 0 014 0 091 0 059 0 004 0 005 φ φ φ φ ...

Page 61: ...36 0 03 2 2 0 1 1 57 0 03 0 768 0 583 0 583 0 768 0 236 0 236 0 197 0 093 0 087 0 062 0 8 0 02 15 12 0 0 05 0 8 0 02 15 12 0 0 05 φ φ φ 0 002 0 001 0 003 0 002 0 002 0 001 0 003 0 002 0 004 0 003 0 004 0 003 0 001 0 002 φ φ φ 0 001 0 002 0 004 0 005 0 001 0 002 Dimensions of mount pad for EV 9200 and that for target device QFP may be different in some parts For the recommended mount pad dimensions...

Page 62: ...x15 9 75 0 026x0 591 0 384 C 0 65 0 026 A 18 4 0 724 D H 0 65x15 9 75 0 026x0 591 0 384 I 11 85 0 467 J 18 4 0 724 E 10 15 0 400 F 12 55 0 494 K C 2 0 C 0 079 L 12 45 0 490 M Q 11 1 0 437 R 1 45 0 057 S 1 45 0 057 N 7 7 0 303 O 10 02 P 14 92 0 587 0 394 W 5 3 0 209 X 4 C 1 0 4 C 0 039 Y 3 55 0 140 T 4 1 3 4 0 051 U 1 8 V 5 0 0 197 0 071 Z 0 9 0 035 7 75 10 25 0 305 0 404 G 14 95 0 589 φ φ φ φ φ φ ...

Page 63: ...onversion Socket Distance Between In Circuit Emulator Conversion Adapter and Conversion Socket or Conversion Adapter EP 753108GC R EV 9200GC 64 700 mm EP 753108GK R TGK 064SBW 700 mm Figure B 4 Distance Between In Circuit Emulator and Conversion Socket or Conversion Adapter 1 Figure B 5 Distance Between In Circuit Emulator and Conversion Socket or Conversion Adapter 2 700 mm In circuit emulator IE...

Page 64: ...circuit emulator IE 75001 R External sense clips Target system Conversion socket EV 9200GC 64 64 pin GC EP 753108GC R Ground clip 35 mm 35 mm 18 5 mm 18 5 mm 8 mm Target system Conversion adapter TGK 064SBW 64 pin GK EP 753108GK R Ground clip Notch Notch In circuit emulator IE 75001 R External sense clips 34 mm 34 mm 18 4 mm 18 4 mm 13 8 mm 9 mm ...

Page 65: ...Document No RA75X Assembler Package Operation U12622E Language U12385E Structured Assembler Preprocessor U12598E Documents Related to Development Tools Hardware User s Manuals Document Name Document No IE 75000 R IE 75001 R In Circuit Emulator EEU 1455 IE 75300 R EM Emulation Board U11354E EP 753108GC R EP 753108GK R Emulation Probe EEU 1495 Documents Related to PROM Writing User s Manuals Documen...

Page 66: ...echnology Manual C10535E Quality Grades on NEC Semiconductor Devices C11531E NEC Semiconductor Device Reliability Quality Control System C10983E Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge ESD C11892E Caution The related documents listed above are subject to change without notice Be sure to use the latest version of each document for designing ...

Page 67: ...µPD75P3116 67 Data Sheet U11369EJ3V0DS MEMO ...

Page 68: ...te No connection for CMOS device inputs can be cause of malfunction If no connection is provided to the input pins it is possible that an internal input level may be generated due to noise etc hence causing malfunction CMOS devices behave differently than Bipolar or NMOS devices Input levels of CMOS devices must be fixed high or low by using a pull up or pull down circuitry Each unused pin should ...

Page 69: ...Kong Ltd Hong Kong Tel 2886 9318 Fax 2886 9022 9044 NEC Electronics Hong Kong Ltd Seoul Branch Seoul Korea Tel 02 528 0303 Fax 02 528 4411 NEC Electronics Shanghai Ltd Shanghai P R China Tel 021 6841 1138 Fax 021 6841 1137 NEC Electronics Taiwan Ltd Taipei Taiwan Tel 02 2719 2377 Fax 02 2719 5951 NEC Electronics Singapore Pte Ltd Novena Square Singapore Tel 253 8311 Fax 250 3583 NEC do Brasil S A ...

Page 70: ...ponsibility for any losses incurred by customers or third parties arising from the use of these circuits software and information While NEC endeavours to enhance the quality reliability and safety of NEC semiconductor products customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely To minimize risks of damage to property or injury including death to pe...

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