NEC mPD78C14 A Schematics Download Page 17 | Manualshive

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µ

PD78C14(A)

17

3.3 Instruction Execution Time

In the following table, one state consists of three clock cycles. So, when the 15 MHz clock is used, one state becomes

200 ns (= 3 x 1/15

µ

s). Execution time of the 4-state instruction, the shortest instruction, becomes 0.8

µ

s.

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Summary of Contents for mPD78C14 A

Page 1: ...ighly accurate 8 bit A D converter Eight analog inputs General purpose serial interface Asynchronous synchronous and I O interface modes Multifunction 16 bit timer event counter Two 8 bit timers I O lines 44 Interrupt functions Three external eight internal Non maskable interrupt 1 Maskable interrupts 10 Zero cross detection function two inputs Standby functions HALT mode Hardware software STOP mo...

Page 2: ...59 58 57 55 54 53 52 51 50 49 48 47 45 44 43 42 41 40 39 38 37 36 35 34 33 56 46 PD78C14G A XXX 36 µ PD2 PD1 PD0 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 ALE WR RD AV DD V AREF AN7 AN6 AN5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 TxD PC1 RxD PC2 SCK PC3 INT2 PC4 TO PC5 CI PC6 CO0 PC7 CO1 NMI PD3 52 PD4 53 PD5 54 PD6 55 PD7 56 STOP 57 VDD 58 PA0 59 PA1 60 PA2 61 PA3 62 PA4 63 PA5 641 2 3 4 5 6 7 8 9 1011...

Page 3: ... PA7 10 PB0 11 PB1 12 PB2 13 PB3 14 PB4 15 PB5 16 PB6 17 PB7 18 PC0 TxD 19 PC1 RxD 20 PC2 SCK 21 PC3 INT2 22 2728 29 30 31323334353637 3839 4041 42 43 9 8 7 6 5 4 3 2 1 68 6766 656463 6261 PD1 PD0 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 ALE WR RD 60 59 58 57 56 55 54 53 52 51 50 49 48 µ PD78C14L A XXX IC 23 PC4 TO 24 PC5 CI 25 PC6 CO0 26 AVDD 47 IC 46 VAREF 45 AN7 44 ...

Page 4: ...BUS ALU 8 16 PSW LATCH LATCH 8 STANDBY CONTROL SYSTEM CONTROL READ WRITE CONTROL VSS VDD STOP RESET MODE1 MODE0 ALE WR RD LATCH INC DEC PC SP EA V B D H A C E L EA V B D H A C E L BUFFER OSC SERIAL I O INT CONTROL TIMER TIMER EVENT COUNTER A D CONVERTER X1 X2 PC0 TxD PC1 RxD PC2 SCK NMI INT1 PC3 INT2 TI PC4 TO PC5 CI AVSS PC7 CO1 PC6 CO0 AN7 0 8 VAREF VDD Note Note DATA MEMORY can only be used whe...

Page 5: ...nnections for Unused Pins 13 3 INSTRUCTION SET 14 3 1 Operand Expression Format Description Method 14 3 2 Instruction Code Description 16 3 3 Instruction Execution Time 17 4 LIST OF MODE REGISTERS 29 5 ELECTRICAL SPECIFICATIONS 30 6 CHARACTERISTIC CURVES reference value 41 7 PACKAGE DRAWINGS 44 8 RECOMMENDED SOLDERING CONDITIONS 47 APPENDIX DEVELOPMENT TOOLS 49 ...

Page 6: ...rent Input leakage current specifications AN7 0 1 µA MAX AN7 0 10 µA MAX Package 64 pin plastic QUIP 64 pin plastic shrink DIP 64 pin plastic QFP 64 pin plastic QUIP 14 x 20 mm thickness 2 05 mm 64 pin plastic QUIP straight 68 pin plastic QFJ 64 pin plastic QFP 14 x 20 mm thickness 2 05 mm 64 pin plastic QFP 14 x 20 mm thickness 2 70 mm 68 pin plastic QFJ ...

Page 7: ...etection pin for AC input PC4 TO Input Output Timer Output Output This pin outputs square waves in which one cycle of the internal clock forms a half cycle indicating the timer s counting time PC5 CI Input Output Counter Input Input This pin inputs external pulse for timer event counter PC6 CO0 Input Output Counter Output 0 1 PC7 CO1 Output This pin outputs programmable square wave by timer event ...

Page 8: ... edge triggering rising edge maskable interrupt This pin is also Interrupt shared with zero cross detection pin for AC input Request AN7 AN0 Input These eight pins input analog signals for the A D converter Pins AN7 AN4 can Analog be used as edge detection falling edge input Input VAREF Input This pin inputs the reference voltage for the A D converter and controls the Reference operation for the A...

Page 9: ...uits of the pins are shown in Table 2 1 and figures from 1 to 11 Table 2 1 Name of Type No Pin Type No Pin Type No PA0 7 5 RESET 2 PB0 7 5 RD 4 PC0 1 5 WR 4 PC2 SCK 8 ALE 4 PC3 INT2 10 STOP 2 PC4 7 5 MODE0 11 PD0 7 5 MODE1 11 PF0 7 5 AN0 3 7 NMI 2 AN4 7 12 INT1 9 VAREF 13 ...

Page 10: ...10 µPD78C14 A Type 4 IN OUT output data output disable Type 1 IN P ch VDD OUT N ch output data output disable N ch P ch VDD IN 1 Type 1 2 Type 2 3 Type 4 4 Type 5 ...

Page 11: ...tput disable self bias enable IN OUT Type 5 Type 2 output data output disable N ch N ch MCC AVSS AVDD AVSS AVDD IN P ch N ch sampling C reference voltage from voltage tap of serial resistor string 5 Type 7 6 Type 8 7 Type 9 8 Type 10 IN Type 1 self bias enable data ...

Page 12: ...12 µPD78C14 A Type 1 IN AVSS STOP Mode P ch 9 Type 11 10 Type 12 11 Type 13 Type 7 Type 2 IN edge detection circuit output data Type 1 N ch IN OUT ...

Page 13: ...Unused Pins Pin Recommended connection PA7 0 PB7 0 PC7 0 Connect to VDD or VSS via resistor PD7 0 PF7 0 RD WR Leave unconnected ALE STOP VDD INT1 NMI Connect to VDD or VSS AVDD Connect to VDD VAREF Connect to VSS AVSS AN7 0 Connect to AVSS or AVDD ...

Page 14: ...M TMM RXB CR0 CR1 CR2 CR3 sr2 PA PB PC PD PF MKH MKL ANM SMH EOM TMM sr3 ETM0 ETM1 sr4 ECNT ECPT rp SP B D H rp1 V B D H EA rp2 SP B D H EA rp3 B D H rpa B D H D H D H rpa1 B D H rpa2 B D H D H D H D byte H A H B H EA H byte rpa3 D H D H D byte H A H B H EA H byte wa 8 bit immediate data word 16 bit immediate data byte 8 bit immediate data bit 3 bit immediate data f CY HC Z irf NMI Note FT0 FT1 F1...

Page 15: ...1 INTFT1 MCC MODE CONTROL C CR3 3 rpa to rpa3 rp addressing F1 INTF1 MF MODE F TXB Tx BUFFER B BC F2 INTF2 MM MEMORY MAPPING RXB Rx BUFFER D DE FE0 INTFE0 TM0 TIMER REG0 SMH SERIAL MODE High H HL FE1 INTFE1 TM1 TIMER REG1 SML SERIAL MODE Low D DE FEIN INTFEIN TMM TIMER MODE MKH MASK High H HL FAD INTFAD ETM0 TIMER EVENT MKL MASK Low D DE FSR INTFSR COUNTER REG0 ZCM ZERO CROSS MODE H HL FST INTFST ...

Page 16: ...MA MB MC MF TXB RXB TM0 TM1 CR0 CR1 CR2 CR3 ZCM S1 0 0 1 1 0 1 1 0 0 1 1 0 0 0 0 1 1 0 1 0 0 1 1 0 0 1 1 0 S0 0 1 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 sr1 sr2 r rpa3 C3 C2 C1 0 0 0 0 1 1 1 1 1 0 0 1 1 0 1 1 1 1 1 1 0 0 1 0 0 1 1 C0 0 1 0 1 1 0 1 0 1 addressing DE HL DE HL DE byte HL A HL B HL EA HL byte irf I3 I2 I1 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 0...

Page 17: ... Execution Time In the following table one state consists of three clock cycles So when the 15 MHz clock is used one state becomes 200 ns 3 x 1 15 µs Execution time of the 4 state instruction the shortest instruction becomes 0 8 µs ...

Page 18: ...MVI MVIW MVIX STAW LDAW STAX LDAX EXX EXA EXH BLOCK DMOV r byte 0 1 1 0 1 R2 R1 R0 sr2 byte 0 1 1 0 0 1 0 0 wa byte 0 1 1 1 0 0 0 1 rpa1 byte 0 1 0 0 1 0 A1 A0 0 1 1 0 0 0 1 1 wa 0 0 0 0 0 0 0 1 wa A3 0 1 1 1 A2 A1 A0 rpa2 A3 0 1 0 1 A2 A1 A0 rpa2 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 1 0 0 0 0 0 0 1 1 0 0 0 1 1 0 1 1 0 1 P1 P0 1 0 1 0 0 1 P1 P0 S3 0 0 0 0 S2 S1 S0 Offset Data Offset Offset Data D...

Page 19: ... 0 1 1 1 0 0 0 0 word word word 0 1 0 0 1 0 0 0 rpa3 1 0 1 1 0 Q2 Q1 Q0 rp1 1 0 1 0 0 Q2 Q1 Q0 rp1 0 P2 P1 P0 0 1 0 0 0 1 0 0 1 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 1 1 0 1 0 1 0 1 0 0 0 1 1 1 1 1 Low Byte Data 14 20 20 20 20 20 14 20 13 10 10 17 8 8 8 8 Note 3 rpa3 EAL rpa3 1 EAH C word B word 1 E word D word 1 L word H word 1 SPL word SPH word 1 EAL rpa3 EAH rpa3 1 SP 1 rp1H SP 2 rp1L SP SP 2 rp1L SP r...

Page 20: ...tion register ANA ORA XRA GTA LTA NEA A r r A A r r A A r r A 1 0 0 1 0 R2 R1 R0 A r 0 0 0 1 r A 0 0 1 1 1 1 1 0 0 1 1 0 0 0 1 1 8 8 8 8 8 8 8 8 8 8 8 8 8 8 A A r r r A A A r r r A A A r r r A A A r r r A A r 1 r A 1 A r r A A r r A ADDNC SUB SBB SUBNB A r A r r A A r r A 1 0 1 0 0 R2 R1 R0 1 0 1 1 0 0 1 0 0 0 0 1 1 0 0 0 1 R2 R1 R0 0 0 0 0 1 0 0 1 1 0 1 1 1 0 1 0 1 R2 R1 R0 No Zero r A No Zero Bo...

Page 21: ...pa rpa rpa 1 0 0 1 0 A2 A1 A0 rpa 1 0 1 0 1 A2 A1 A0 rpa 1 1 0 0 1 1 0 1 1 1 1 0 11 11 11 11 11 11 11 11 11 11 11 11 11 A A rpa A A rpa A A rpa CY A A rpa A A rpa A A rpa A A rpa A rpa 1 A rpa A rpa A rpa A rpa EQA ONA ADDX ADDNCX rpa rpa rpa rpa 1 1 1 1 1 R2 R1 R0 1 1 1 1 1 1 1 0 1 0 0 1 1 1 1 1 1 0 1 1 1 0 0 0 1 A2 A1 A0 1 0 1 0 1 0 1 1 Zero rpa No Zero Zero Borrow No Borrow No Carry Zero No Bor...

Page 22: ...1 1 0 1 0 0 r byte 0 1 1 0 sr2 byte 0 1 1 1 0 1 1 0 A byte 0 1 1 1 0 1 0 0 r byte 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 1 0 1 0 0 0 1 1 0 0 0 0 0 0 1 1 1 0 1 1 1 0 1 0 0 Data Data 7 11 20 7 11 20 7 11 20 7 11 20 7 11 A A byte r r byte sr2 sr2 byte A A byte r r byte sr2 sr2 byte A A byte CY r r byte CY sr2 sr2 byte CY A A byte r r byte sr2 sr2 byte r r byte sr2 byte A byte r byte sr2 byte A byte r byte Dat...

Page 23: ...1 0 1 1 1 A byte 0 1 1 1 0 1 0 0 r byte 0 1 1 0 sr2 byte 0 1 1 0 0 1 1 1 A byte 0 1 1 1 0 1 0 0 0 1 1 0 0 1 1 1 0 1 1 1 0 1 1 1 0 1 0 0 0 1 1 0 Data Data 7 11 20 7 11 14 7 11 A byte 1 r byte 1 sr2 byte 1 A byte r byte sr2 byte A byte r byte sr2 byte A byte r byte sr2 byte r byte sr2 byte A byte r byte sr2 byte Data Data Data 0 0 0 1 0 R2 R1 R0 S3 0 0 1 0 S2 S1 S0 Data 0 0 1 0 1 R2 R1 R0 S3 0 1 0 1...

Page 24: ...0 1 1 1 0 1 0 0 wa wa wa wa wa wa wa Data 14 14 14 14 14 14 14 14 14 14 14 14 14 14 A A V wa A A V wa CY A A V wa A A V wa A A V wa A A V wa A A V wa A A V wa A V wa 1 A V wa A V wa A V wa A V wa wa wa wa wa wa wa Data 0 1 0 1 1 R2 R1 R0 S3 1 0 1 1 S2 S1 S0 Data 1 1 0 1 1 0 1 0 1 1 1 1 1 0 1 1 1 0 0 1 1 0 0 1 0 0 0 0 1 0 1 1 1 1 1 0 1 1 0 0 Data offset No Zero Zero No Borrow No Zero Borrow EQAW NE...

Page 25: ...13 13 11 11 11 11 11 11 11 11 11 11 V wa byte V wa byte V wa byte EA EA r2 EA EA rp3 EA EA rp3 CY EA EA rp3 EA EA r2 EA EA rp3 EA EA rp3 CY EA EA rp3 EA EA rp3 OFFAW ORIW LTIW EQIW EA rp3 EA rp3 EA rp3 EA rp3 1 1 0 1 1 0 0 0 1 0 1 1 1 1 1 1 1 1 0 1 0 1 0 0 0 0 R1 R0 1 1 1 0 0 1 P1 P0 EA rp3 Zero Borrow No Borrow No Carry No Borrow No Zero Zero Zero No Zero GTIW NEIW ONIW EADD DADC DSUBNB DAN DOR 0...

Page 26: ...r2 r2 1 V wa V wa 1 rp rp 1 EA EA 1 r2 r2 1 V wa V wa 1 rp rp 1 EA EA 1 Decimal Adjust Accumulator CY 1 DGT DNE DON MUL rp 1 0 1 0 1 1 P1 P0 EA Carry Borrow No Borrow No Zero Zero Zero No Zero DEQ DOFF DIV INRW STC CLC NEGA CY 0 16 bit arithmetic operation DLT 0 0 1 1 1 0 1 0 8 A A 1 0 1 0 0 1 0 0 0 Multiply divide Other arithmetic operation 0 1 0 1 0 0 R1 R0 0 0 1 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 1 ...

Page 27: ...1 EAn EA0 0 CY EA15 EAn 1 EAn EA15 0 CY EA0 PC word PCH B PCL C PC PC 1 jdisp 1 PC PC 2 jdisp PC EA SP 1 PC 3 H SP 2 PC 3 L PC word SP SP 2 RLD RLL SLL SLLC word 0 0 1 1 1 0 0 0 word Carry RLR SLR SLRC DRLR CALL CALB CALF SP 1 PC 2 H SP 2 PC 2 L PCH B PCL C SP SP 2 Rotation shift RRD 13 SP 1 PC 2 H SP 2 PC 2 L PC15 11 00001 PC10 0 fa SP SP 2 Call 0 1 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1...

Page 28: ...ffset 0 1 1 1 0 0 1 0 1 0 0 1 Call Return CPU operation 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 0 1 0 1 1 B2 B1 B0 0 1 0 0 1 0 0 0 ta 0 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 0 1 0 I4 I3 I2 I1 I0 0 1 1 I4 I3 I2 I1 I0 0 0 0 0 1 F2 F1 F0 0 0 0 1 f 1 f 0 irf 1 irf 0 PCL SP PCH SP 1 SP SP 2 PCL SP PCH SP 1 SP SP 2 PC PC n Notes 1 B2 Data is applied for rpa2 D byte or H byte 2 B3 Data is applied for rpa...

Page 29: ...ts D and F MF MODE F W Specifies input output of Port F set in the port mode in bit units TMM Timer mode R W Specifies operation mode of the timer ETMM Timer Event W Specifies operation mode of the Timer Event Counter Counter Mode EOM Timer Event R W Controls output level of CO0 and CO1 Counter Output Mode SML Serial Mode W Specifies operation mode of the serial interface SMH R W MKL Interrupt Mas...

Page 30: ...n 4 0 mA All Output Pin Total 100 mA Output Current High IOH All Output Pin 2 0 mA All Output Pin Total 50 mA A D Converter VAREF 0 5 to AVDD 0 3 V Reference Input Voltage Operating Ambient TA 40 to 85 C Temperature Storage Temperature Tstg 65 to 150 C Caution If any of the parameters exceeds the absolute maximum ratings even for a moment this may damage product quality The absolute maximum rating...

Page 31: ... Converter 5 8 15 MHz Used X1 Input 0 20 ns Rise Fall Time tr tf X1 Input High Low 20 250 ns Level Width tøH tøL Cautions 1 Oscillator circuit should be in the nearest area from X1 and X2 pins 2 Do not place other signal lines within the area enclosed with broken lines Note For a crystal resonator the following external capacitances are recommended C1 C2 10 pF CAPACITANCE TA 25 C VDD VSS 0 V Param...

Page 32: ...urrent II INT1 Note 1 TI PC3 Note 2 0 V VI VDD 200 µA Input Leakage ILI All except INT1 TI PC3 AN7 to AN0 0 V VI VDD 10 µA Current AN7 to AN0 0 V VI VDD 1 µA Output Leakage ILO 0 V VO VDD 10 µA Current AVDD Supply AIDD1 Operation Mode fxx 15 MHz 0 5 1 3 mA Current AIDD2 STOP Mode 10 20 µA VDD Supply Current IDD1 Operation mode fxx 15 MHz 16 30 mA IDD2 HALT Mode fxx 15 MHz 8 15 mA Data Retention VD...

Page 33: ...me tLR 15 ns Data Hold Time after RD tRDH CL 150 pF 0 ns RD ALE Delay Time tRL fxx 15 MHz CL 150 pF 80 ns RD Width Low tRR Data Read 215 ns fxx 15 MHz CL 150 pF OP code Fetch 415 ns fxx 15 MHz CL 150 pF ALE Width High tLL fxx 15 MHz CL 150 pF 90 ns M1 Setup Time to ALE tML fxx 15 MHz 30 ns M1 Hold Time after ALE tLM 35 ns IO M Setup Time to ALE tIL 30 ns IO M Hold Time after ALE tLI 35 ns Address ...

Page 34: ...f x16 or x64 clock rate in asynchronous mode Remark The numeric values in the table apply when fXX 15 MHz CL 150 pF ZERO CROSS CHARACTERISTICS Parameter Symbol Test Condition MIN MAX UNIT Zero Cross Detection Input VZX AC Coupled 1 1 8 VACP P Zero Cross Accuracy AZX 60 Hz Sine Wave 135 mV Zero Cross Detection Input Frequency fZX 0 05 1 kHz OTHER OPERATION Parameter Symbol Test Condition MIN MAX UN...

Page 35: ...o 70 C 0 4 FSR 4 0 V VAREF AVDD 66 ns tCYC 170 ns Conversion time tCONV 66 ns tCYC 110 ns 576 tCYC 110 ns tCYC 170 ns 432 tCYC Sampling Time tSAMP 66 ns tCYC 110 ns 96 tCYC 110 ns tCYC 170 ns 72 tCYC Analog Input Voltage VIAN AN7 0 include unused pins 0 VAREF V Analog Input Impedance RAN 50 MΩ Reference Voltage VAREF 3 4 AVDD V VAREF Current IAREF1 Operation mode 1 5 3 0 mA IAREF2 STOP mode 0 7 1 ...

Page 36: ...0 MIN ns tLDW T 110 MAX ns tLW T 50 MIN ns tDW 4T 100 MIN ns tWDH 2T 70 MIN ns tWL 2T 50 MIN ns tWW 4T 50 MIN ns tCYK 6T SCK Input Note 1 12T SCK Input Note 2 MIN ns 24T SCK Output tKKL 2 5T 5 SCK Input Note 1 5T 5 SCK Input Note 2 MIN ns 12T 100 SCK Output tKKH 2 5T 5 SCK Input Note 1 5T 5 SCK Input Note 2 MIN ns 12T 100 SCK Output Notes 1 In case of x16 or x64 clock rate in asynchronous mode 2 I...

Page 37: ...ion Notes 1 M1 signal is output to MODE1 pin at first OP code fetch cycle if MODE1 pin is pulled up 2 IO M signal is output to MODE0 pin at sr to sr2 register read cycle if MODE0 pin is pulled up 3 IO M signal is output to MODE0 pin at sr to sr2 register write cycle if MODE0 pin is pulled up tLL tLA tDW tWDH tWL tWW tWD tLW tAW tAL tLI tIL X1 PF7 0 PD7 0 ALE WR MODE0 IO M Note 3 address high order...

Page 38: ...4 A 38 tTIL TI tTIH Serial Operation Timer Input Timing Timer Event Counter Input Timing tKKL tKKH tCYK tKRX SCK TXD RXD tKTX tRXK tCI1L CI tCI2L CI tCI2H Event Counter Mode Pulse Width Measurement Mode tCI1H ...

Page 39: ...µPD78C14 A 39 Interrupt Input Timing RESET Input Timing External Clock Timing tNIL NMI tNIH tI2L INT2 tI2H INT1 tI1H tI1L X1 tφH 0 8VDD 0 8 V t t tφL tCYC r f tRSL RESET tRSH 0 8VDD 0 2VDD ...

Page 40: ...ta retention power supply voltage VDDDR 2 5 5 5 V Data retention power supply current IDDDR VDDDR 2 5 V 1 15 µA VDDDR 5 V 10 10 50 µA VDD rise fall time tRVD tFVD 200 µs STOP setup time to VDD tSSTVD 12TNote 0 5 µs STOP hold time to VDD tHVDST 12TNote 0 5 µs Note T tCYC 1 fxx Data Retention Timing VDD STOP tFVD tSSTVD VDDDR tRVD tHVDST VIH2 VIL2 90 10 ...

Page 41: ...6 0 10 15 20 IDD1 TYP IDD1 IDD2 vs VDD TA 25 C fXX 15 MHz Supply Voltage VDD V V DD Supply Current I DD1 I DD2 mA IDD1 TYP 0 5 10 15 0 10 20 IDD1 IDD2 vs fXX TA 25 C VDD 5 V Oscillation Frequency fXX MHz V DD Supply Current I DD1 I DD2 mA 0 5 25 30 IDD2 TYP 30 IDD2 TYP ...

Page 42: ... 2 0 TYP IOL vs VOL TA 25 C VDD 5 V Output Low Voltage VOL V Output Low Current I OL mA 0 0 5 2 5 0 5 0 0 1 0 2 0 3 0 4 1 0 1 5 TYP IOH vs VOH TA 25 C VDD 5 V Supply Voltage Output High Voltage VDD VOH V Output High Current I OH mA 0 0 5 0 5 ...

Page 43: ...µPD78C14 A 43 0 2 3 4 5 4 6 8 TYP IDDDR vs VDDDR TA 25 C Data Retention Supply Voltage VDDDR V Data Retention Supply Current I DDDR A 0 2 10 6 µ ...

Page 44: ... 157 1 634 NOTE X 4 0 0 750 Each lead centerline is located within 0 25 mm 0 010 inch of its true position T P at maxi mum material condition 0 142 0 043 0 020 24 13 0 950 0 010 0 25 2 54 T P 0 004 0 005 0 011 0 006 0 012 0 008 0 004 0 005 41 5 0 3 0 2 0 50 0 10 1 1 0 25 0 15 0 10 0 05 0 3 3 6 0 1 1 05 19 05 1 05 0 650 0 004 0 003 0 013 0 012 0 042 0 042 64 PIN PLASTIC QUIP ...

Page 45: ...0 10 0 20 20 0 0 2 0 929 0 016 0 039 0 039 0 008 0 039 T P 0 795 NOTE M N 0 12 0 15 1 8 0 2 1 0 T P 0 005 0 006 0 004 0 003 Each lead centerline is located within 0 20 mm 0 008 inch of its true position T P at maximum material condition 0 071 0 016 0 551 0 8 0 2 0 031 P 2 7 0 106 0 693 0 016 17 6 0 4 1 0 0 009 0 008 Q 0 1 0 1 0 004 0 004 S 3 0 MAX 0 119 MAX 0 10 0 05 0 009 0 008 0 004 0 005 0 009 ...

Page 46: ...J K M N P Q T U 25 2 0 2 24 20 24 20 25 2 0 2 1 94 0 15 0 6 4 4 0 2 2 8 0 2 0 9 MIN 3 4 1 27 T P 0 40 1 0 0 12 23 12 0 20 0 15 R 0 8 0 20 0 10 0 05 0 992 0 008 0 953 0 953 0 992 0 008 0 076 0 024 0 173 0 110 0 035 MIN 0 134 0 050 T P 0 016 0 005 0 910 0 006 R 0 031 0 008 0 009 0 008 0 009 0 008 0 004 0 005 0 004 0 002 0 009 0 008 N K M Q A U 68 B D C 1 F E T P M G H I J 68 PIN PLASTIC QFJ 950 mil ...

Page 47: ... has come down to the room temperature from the heating from the first reflow 2 Do not wash the soldered portion with the flux following the first reflow Wave soldering Soldering bath temperature 260 C or less Time Within 10 s WS60 00 1 Count Once Preheating temperature 120 C MAX package surface temperature Partial heating Pin temperature 300 C or less Time Within 3 s per pin row Caution Do not us...

Page 48: ...ldering Method Soldering Conditions Wave Soldering pin part only Soldering bath temperature 260 C or less Time Within 10 s Partial heating Pin temperature 300 C or less Time Within 3 s per pin row Caution Apply wave soldering only to pins and be careful not to bring solder directly in contact with the package ...

Page 49: ...o program single chip microcontrollers ware containing PROM by stand alone or host machine operation by connecting an attached board and optional programmer adapter to PG 1500 It also enables you to program typical PROM devices of 256 Kbits to 4 Mbits PA 78CP14GQ PROM programmer adapter for the µPD78CP14 A and connected to PG 1500 for use Soft PG 1500 PG 1500 and a host machine are connected by a ...

Page 50: ... debugging Soft IE 78C11 M IE 78C11 M and a host machine are connected by RS 232 C and IE 78C11 M is controlled ware control program on the host machine IE controller Host machine Ordering code OS Distribution media product name PC 9800 series MS DOS 3 5 inch 2HD µS5A13IE78C11 Ver 2 11 to Ver 3 30D 5 inch 2HD µS5A10IE78C11 IBM PC AT PC DOS 5 inch 2HC µS7B10IE78C11 Ver 3 1 Remark Operation of IE co...

Page 51: ...nction If no connection is provided to the input pins it is possible that an internal input level may be generated due to noise etc hence causing malfunction CMOS device behave differently than Bipolar or NMOS devices Input levels of CMOS devices must be fixed high or low by using a pull up or pull down circuitry Each unused pin should be connected to VDD or GND with a resistor if it is considered...

Page 52: ...application The recommended applications of a device depend on its quality grade as indicated below Customers must check the quality grade of each device before using it in a particular application Standard Computers office equipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industri...

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