µ
PD78C14(A)
32
DC CHARACTERISTICS (T
A
= –40 to +85 ˚C, V
DD
= AV
DD
= +5.0 V
±
10 %, V
SS
= AV
SS
= 0 V)
Parameter
Symbol
Test Condition
MIN.
TYP.
MAX.
UNIT
Input Low Voltage
V
IL1
All except RESET, STOP, NMI, SCK, INT1,
0
0.8
V
TI, AN7 to AN4
V
IL2
RESET, STOP, NMI, SCK, INT1, TI, AN7 to AN4 0
0.2V
DD
V
Input High Voltage
V
IH1
All except RESET, STOP, NMI, SCK, INT1,
2.2
V
DD
V
TI, AN7 to AN4, X1, X2
V
IH2
RESET, STOP, NMI, SCK, INT1, TI, AN7 to
0.8V
DD
V
DD
V
AN4, X1, X2
Output Low Voltage
V
OL
I
OL
= 2.0 mA
0.45
V
Output High Voltage
V
OH
I
OH
= –1.0 mA
V
DD
–
1.0
V
I
OH
= –100
µ
A
V
DD
–
0.5
V
Input Current
I
I
INT1
Note 1
, TI (PC3)
Note 2
; 0 V
≤
V
I
≤
V
DD
±
200
µ
A
Input Leakage
I
LI
All except INT1, TI (PC3), AN7 to AN0; 0 V
≤
V
I
≤
V
DD
±
10
µ
A
Current
AN7 to AN0; 0 V
≤
V
I
≤
V
DD
±
1
µ
A
Output Leakage
I
LO
0 V
≤
V
O
≤
V
DD
±
10
µ
A
Current
AV
DD
Supply
AI
DD1
Operation Mode f
xx
= 15 MHz
0.5
1.3
mA
Current
AI
DD2
STOP Mode
10
20
µ
A
V
DD
Supply Current
I
DD1
Operation mode f
xx
= 15 MHz
16
30
mA
I
DD2
HALT Mode f
xx
= 15 MHz
8
15
mA
Data Retention
V
DDDR
Hardware/Software STOP Mode
2.5
V
Voltage
Data Retention
I
DDDR
Hardware/Software
Note 3
V
DDDR
= 2.5 V
1
15
µ
A
Current
STOP Mode
V
DDDR
= 5 V
±
10 %
10
50
µ
A
Notes 1.
When self-bias is generated by ZCM register.
2.
When set in the control mode by MCC register and self-bias is generated by ZCM register.
3.
When self-bias is not generated.
*
