NEC LCD1550X-BK, Service Manual

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1.7 Panel interface
• Timing for panel power and interface signal
The following is set to satisfy the following panel AC timing with the microcomputer timing
control.
t1
<
=
40ms
0ms < t2
<
=
50ms
0ms < t3
<
=
3ms
0ms < t4
<
=
3ms
0ms < t5
<
=
50ms
0ms < t6
<
=
1s
t7 0.2s
• DC characteristics of interface signal.
The ASIC (Maurice2) clock delay time is set so that the panel clock's falling edge hits at the
center of the data.
The timing reference is 1.5V.
Note that the panel input Hi level voltage (VIH) and panel input Lo level voltage (VIL) are as
follows.
VIH 2.0V, VIL
<
=
0.8V (TTL level)
Maurice2's panel output level is VOH D3_3V-0.05V and VOL
<
=
0.05V, and thus direct
connection is possible.
* D3_3V is Maurice2's I/O power 3.3V.
PANEL5V
Interface signal
(3.3V system)
t
1
t
2
t
3
t
4
t
5
t
6 t
7
1.5V
1.5V
1.5V
TSTC THTC
QCLK
QDE, QHD,
QVD, DATA