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• Digital signal DVI-I (D) and analog signal (DVI-I (A), D-SUB) switching
The microcomputer sets the ASIC internal input switching switcher (SOURCE register) to
"external digital" for DVI-I (D), "analog 1" for DVI-I (A), and to "analog 2" for D-SUB.
• The frequency and resolution (for digital signal) of the selected input signal are measured by
ASIC.
For analog signal input: (Pin 148 : AH1, Pin 149 : AV1, Pin 146 : AH2, Pin 147 : AV2)
For digital signal input: (Pin 151 : DCLK, Pin 153 : DE, Pin 154 : DV, Pin 155 : DH)
• The DVI-I (D) and DVI-I (A) input selection follows the following order of priority. Selection of
input signal is controlled.
Input signal
DVI-I (A)
DVI-I (D)
During PMS
/ PD
Hi
Hi
Cycle pulse
*1
Order of priority
2
1
-
*1 : 50msec interval "Hi" for both input 1 and 2. Control is
carried out at an intermittent interval such as 450msec interval
"Lo".
Summary of Contents for LCD1550X-BK
Page 88: ...SCHEMATIC DIAGRAM POWER LCD1550X Normal Power Save 1ch Pin 4 2ch Pin 1 3ch Pin 2 4ch Pin 5 ...
Page 89: ...SCHEMATIC DIAGRAM PWB MAIN POWER LCD1550X ...
Page 90: ...SCHEMATIC DIAGRAM PWB MAIN INPUT LCD1550X ...
Page 91: ...SCHEMATIC DIAGRAM PWB MAIN SYNC LCD1550X ...
Page 92: ...SCHEMATIC DIAGRAM PWB MAIN TMDS LCD1550X ...
Page 96: ...SCHEMATIC DIAGRAM PWB MAIN ASIC LCD1550X ...
Page 97: ...SCHEMATIC DIAGRAM INVERTER LCD1550X 1ch Q701 B 2ch Q702 B ...
Page 98: ...SCHEMATIC DIAGRAM PWB SW LCD1550X ...
Page 100: ...SCHEMATIC DIAGRAM POWER LCD1550X ...
Page 101: ...SCHEMATIC DIAGRAM PWB MAIN POWER LCD1550X ...
Page 102: ...SCHEMATIC DIAGRAM PWB MAIN INPUT LCD1550X ...
Page 103: ...SCHEMATIC DIAGRAM PWB MAIN SYNC LCD1550X ...
Page 104: ...SCHEMATIC DIAGRAM PWB MAIN TMDS LCD1550X ...
Page 105: ...SCHEMATIC DIAGRAM PWB MAIN MC LCD1550X ...
Page 106: ...SCHEMATIC DIAGRAM PWB MAIN ASIC LCD1550X ...
Page 107: ...SCHEMATIC DIAGRAM INVERTER LCD1550X ...
Page 108: ...SCHEMATIC DIAGRAM PWB SW LCD1550X ...
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