NEC IE-703242-G1-EM1, Preliminary User'S Manual

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Chapter 4 Differences between Target Device and Emulation Board
Preliminary User’s Manual U16345EE1V0UM00
100
Pin
Top pin
name
Pin Function
default I/O
single chip
Emulated by
Venus chip
Emulated by
FPGA via Level
Shifter
Alternative
connected to:
34 P51 P51 I Venus
35 P52 P52 I Venus
36 P53 P53 I Venus
37 P54 P54/DCTXD0 I Venus
38 P55 P55/DCRXD0 I Venus
39 P56 P56 I Venus
40 P57 P57 I Venus
41 PCS0 PCS0 I FPGA via L/S
42 PCS1 PCS1 I FPGA via L/S
43 PDL0 PDL0 I FPGA via L/S
44 PDL1 PDL1 I FPGA via L/S
45 PDL2 PDL2 I FPGA via L/S
46 PDL3 PDL3 I FPGA via L/S
47 PDL4 PDL4 I FPGA via L/S
48 PDL5 PDL5 I FPGA via L/S
49 PDL6 PDL6 I FPGA via L/S
50 PDL7 PDL7 I FPGA via L/S
51 PDL8 PDL8 I FPGA via L/S
52 PDL9 PDL9 I FPGA via L/S
53 PDL10 PDL10 I FPGA via L/S
54 PDL11 PDL11 I FPGA via L/S
55 PDL12 PDL12 I FPGA via L/S
56 PDL13 PDL13 I FPGA via L/S
57 V
PP
V
PP
S not connected
58 PDL14 PDL14 I FPGA via L/S
59 PDL15 PDL15 I FPGA via L/S
60 V
DD51
V
DD51
S buffered
61 V
SS51
V
SS51
S Ground
62 PCM0 PCM0 I FPGA via L/S
63 PCM1 PCM1, CLOCKOUT I FPGA via L/S
64 PCM2 PCM2 I FPGA via L/S
65 V
SS31
V
SS31
S Ground
66 REGC1 REGC1 S not connected
67 PCM3 PCM4 I FPGA via L/S
68 PDH0 PDH0 I FPGA via L/S
69 PDH1 PDH1 I FPGA via L/S
70 PDH2 PDH2 I FPGA via L/S
71 PDH3 PDH3 I FPGA via L/S
72 PDH4 PDH4 I FPGA via L/S
Table 4-1: Pin list according to their emulation location (2/3)