NEC Barracuda, Service Manual

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Barracuda PDA Maintenance
72
4. Pin Descriptions of Major Components
4.1 Intel® StrongARM* SA-1110 Microprocessor-1
The following table describes the signals.
Key to Signal Types: n
– Active low signal
IC – Input, CMOS threshold
ICOCZ – Input, CMOS threshold, output CMOS levels, tristatable
OCZ – Output, CMOS levels, tristatable
Signal Descriptions
Name Type Description
A 25:0 OCZ Memory address bus. This bus signals the address requested for
memory accesses.
Bits 24..10 carry the 15-bit DRAM address. The static memory
devices and the expansion bus receive address bits 25..0.
D 31:0
ICOCZ Memory data bus. Bits 15..0 are used for 16-bit data busses.
nCS 5:0 OCZ Static chip selects. These signals are chip selects to static memory
devices such as ROM and Flash. They are individually programmable
in the memory configuration registers. Bits 5..3 can be used with
variable latency I/O devices.
RDY IC Static data ready signal for nCS 5:3. This signal should be connected
to the data ready output pins of variable latency I/O devices that
require variable data latencies. Devices selected by nCS 5:3 can share
the RDY pin if they drive it high prior to tristating and a weak
external pull-up is present.
nOE OCZ Memory output enable. This signal should be connected to the output
enables of memory devices to control their data bus drivers.
nWE OCZ Memory write enable. This signal should be connected to the write
enables of memory devices.This signal is used in conjunction with
nCAS 3:0 to perform byte writes.
nRAS 3:0/
nSDCS 3:0 OCZ DRAM RAS or SDRAM CS for banks 0 through 3. These signals
should be connected to the row address strobe (RAS) pins for
asynchronous DRAM or the chip select (CS) pins for SDRAM.
nCAS 3:0/
DQM 3:0 OCZ DRAM CAS or SDRAM DQM for data banks 0 through 3. These
signals should be connected to the column address strobe (CAS) pins
for asynchronous DRAM or the data output mask enables (DQM) for
SDRAM.
nSDRAS OCZ SDRAM RAS. This signal should be connected to the row address
strobe (RAS) pins for all banks of SDRAM.
nSDCAS
OCZ SDRAM CAS. This signal should be connected to the column address
strobe (CAS) pins for all banks of SDRAM.