![background image](http://html1.mh-extra.com/html/national-semiconductor/dp83816avng/dp83816avng_manual_710451067.webp)
66
www.national.com
4.0 Register Set
(Continued)
DP83816
4.3 Internal PHY Registers
The Internal Phy Registers are only 16 bits wide. Bits [31:16] are not used. In the following register definitions under the
‘Default’ heading, the following definitions hold true:
— RW=
R
ead
W
rite access
— RO=
R
ead
O
nly access
— LL=
L
atched
L
ow and held until read, based upon the occurrence of the corresponding event
— LH=
L
atched
H
igh and held until read, based upon the occurrence of the corresponding event
— SC=Register sets on event occurrence and
S
elf-
C
lears when event ends
— P=Register bit is
P
ermanently set to a default value
— COR=
C
lear
O
n
R
ead
4.3.1 Basic Mode Control Register
Tag:
BMCR
Size:
16 bits
Hard Reset:
XX00h
Offset:
0080h
Access:
Read Write
Bit
Bit Name
Description
15
Reset
Reset:
Default: 0, RW/SC
1 = Initiate software Reset / Reset in Process
0 = Normal operation
This self-clearing bit returns a value of one until the reset process is complete. A reset causes all PHY
registers to return to their default values (in some cases registers defaults are defined by related bits in
the CFG register, offset 04h).
14
Loopback
Loopback:
Default: 0
1 = Loopback enabled
0 = Normal operation
The loopback function enables MII transmit data to be routed to the MII receive data path.
Setting this bit may cause the de-scrambler to lose synchronization and produce a 500
µ
s “dead time”
before any valid data will appear at the MII receive outputs.
13
Speed
Selection
Speed Select:
Default: dependent on the setting of the ANEG_SEL bits in the CFG register
When auto-negotiation is disabled writing to this bit allows the port speed to be selected.
1 = 100 Mb/s
0 = 10 Mb/s
12
Auto-
Negotiation
Enable
Auto-Negotiation Enable:
Default: dependent on the setting of the ANEG_SEL bits in the CFG register
1 = Auto-Negotiation Enabled - bits 8 and 13 of this register are ignored when this bit is set.
0 = Auto-Negotiation Disabled - bits 8 and 13 determine the port speed and duplex mode.
11
Power Down
Power Down:
Default: 0
1 = Power down
0 = Normal operation
Setting this bit powers down the port.
10
Isolate
Isolate:
Default: 0
1 = Isolates the port from the MII with the exception of the serial management.
0 = Normal operation
9
Restart Auto-
Negotiation
Restart Auto-Negotiation:
Default: 0, RW/SC
1 = Restart Auto-Negotiation
0 = Normal operation
When this bit is set, it re-initiates the Auto-Negotiation process. If Auto-Negotiation is disabled (bit 12 =
0), this bit is ignored. This bit is self-clearing and will remain a value of 1 until Auto-Negotiation is initiated,
whereupon it will self-clear. Operation of the Auto-Negotiation process is not affected by the management
entity clearing this bit.
8
Duplex Mode
Duplex Mode:
Default: dependent on the setting of the ANEG_SEL bits in the CFG register
When auto-negotiation is disabled writing to this bit allows the port Duplex capability to be selected.
1 = Full Duplex operation
0 = Half Duplex operation
Summary of Contents for DP83816AVNG
Page 106: ...105 www national com DP83816 Notes...